Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : dti_and2
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00

Source File(s) :
/nfs_project/gemini/DV/mahmood/all_tests_main/gemini/design/ip/dti/libs/dti_tm28hpcp_ddr4_phy/hdl/library/dti_tm28hpcp_l30_stdcells_10t_rev1p0p3.v

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst51.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst55.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst59.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst74.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst84.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst97.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst98.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst106.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst113.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst118.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst136.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst158.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst174.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst181.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst192.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst211.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst235.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst246.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst253.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst257.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst272.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst284.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst288.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst291.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst337.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst338.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst340.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst368.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst377.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst383.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst392.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst404.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst420.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst453.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst468.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst469.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst470.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst487.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst488.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst503.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst527.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst529.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst556.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst559.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst561.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst565.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst566.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst568.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst577.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst586.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst594.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst603.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst604.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst606.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst626.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst633.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst641.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst649.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst651.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst661.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst679.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst710.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst722.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst724.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst736.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst743.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst754.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst767.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst783.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst806.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst807.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst816.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst818.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst833.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst841.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst844.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst860.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst863.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst869.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst870.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst872.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst878.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst885.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst888.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst897.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst907.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst918.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst922.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst932.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst936.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst938.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst954.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst963.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst971.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst981.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1006.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1022.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1023.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1024.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1027.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1040.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1043.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1075.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1092.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1119.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1127.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1135.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1142.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1171.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1172.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1177.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1193.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1207.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1221.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1244.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1253.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1256.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1260.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1265.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1268.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1271.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1272.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1281.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1284.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1286.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1287.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1290.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1295.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1307.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1315.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1317.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1318.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1344.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1346.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1351.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1361.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1362.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1384.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1385.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1390.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1392.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1409.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1420.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1432.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1446.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1455.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1484.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1504.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1520.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1553.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1566.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1581.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1604.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1616.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1631.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1634.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1637.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1642.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1645.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1652.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1660.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1666.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1678.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1689.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1715.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1717.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1724.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1729.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1733.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1745.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1760.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1761.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1822.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1823.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1887.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1894.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1950.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1963.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1966.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1968.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1971.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1973.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1974.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1994.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1995.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2001.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2004.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2017.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2021.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2038.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2046.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2047.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2048.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2060.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2077.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2082.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2091.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2092.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2106.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2114.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2130.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2133.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2134.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2146.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2147.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2158.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2166.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2185.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2212.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2214.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2232.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2261.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2265.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2271.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2293.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2305.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2318.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2331.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2343.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2348.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2358.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2366.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2376.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2379.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2383.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2390.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2407.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2424.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2434.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2461.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2464.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2468.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2485.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2518.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2534.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2560.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2576.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2584.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2601.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2614.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2622.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2625.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2636.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2646.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2652.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2653.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2659.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2675.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2686.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2692.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2696.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2702.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2704.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2707.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2716.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2727.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2743.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2753.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2759.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2771.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2785.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2788.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2797.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2801.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2804.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2827.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2834.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2838.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2843.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2862.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2875.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2880.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2889.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2904.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2910.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2954.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2961.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2972.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2981.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3015.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3023.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3040.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3070.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3076.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3095.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3097.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3108.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3109.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3115.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3125.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3143.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3156.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3158.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3163.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3218.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3229.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3238.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3270.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3281.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3285.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3303.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3311.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3318.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3322.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3324.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3330.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3338.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3339.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3341.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3351.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3356.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3359.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3362.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3368.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3370.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3378.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3384.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3421.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3422.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3427.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3432.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3444.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3446.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3448.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3489.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3492.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3496.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3497.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3498.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3534.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3536.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3552.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3561.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3583.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3592.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3606.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3626.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3627.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3647.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3654.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3662.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3681.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3684.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3686.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3712.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3728.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3755.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3760.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3763.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3779.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3786.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3795.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3806.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3813.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3822.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3833.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3839.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3854.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3859.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3863.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3869.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3883.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3888.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3894.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3902.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3913.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3921.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3929.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3939.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3967.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3989.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3992.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4005.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4006.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4011.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4034.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4040.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4072.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4080.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4083.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4084.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4089.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4091.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4092.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4102.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4115.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4137.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4141.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4147.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4162.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4185.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4191.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4204.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4213.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4217.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4237.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4255.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4266.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4268.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4272.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4291.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4294.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4297.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4303.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4307.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4314.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4331.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4357.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4360.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4370.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4376.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4382.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4405.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4411.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4412.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4413.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4438.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4466.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4478.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4485.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4486.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4495.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4511.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4518.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4519.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4540.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4561.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4566.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4568.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4569.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4570.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4573.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4576.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4581.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4587.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4597.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4608.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4615.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4624.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4638.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4651.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4655.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4656.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4660.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4663.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4675.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4676.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4683.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4720.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4744.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4763.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4769.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4801.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4811.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4820.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4825.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4826.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4831.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4838.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4853.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4875.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4881.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4886.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4898.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4900.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4904.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4908.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4921.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4935.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4943.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4947.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4966.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4978.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4980.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5000.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5006.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5012.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5023.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5050.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5062.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5066.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5069.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5070.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5094.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5097.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5135.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5143.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5152.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5163.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5170.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5176.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5205.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5216.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5218.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5228.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5252.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5257.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5264.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5281.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5289.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5295.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5306.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5307.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5315.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5320.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5325.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5330.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5340.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5403.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5417.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5430.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5450.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5457.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5465.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5469.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5470.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5474.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5484.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5485.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5501.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5505.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5535.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5564.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5566.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5572.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5580.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5582.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5607.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5612.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5615.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5630.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5648.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5658.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5663.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5666.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5680.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5695.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5718.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5727.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5747.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5771.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5784.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5785.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5807.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5813.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5822.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5825.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5830.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5833.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5870.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5882.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5888.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5894.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5902.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5910.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5911.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5912.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5913.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5914.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5918.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5921.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5936.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5954.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5962.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5964.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5999.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6015.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6018.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6019.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6031.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6060.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6094.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6098.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6108.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6124.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6144.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6145.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6148.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6170.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6185.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6208.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6210.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6220.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6272.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6279.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6319.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6326.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6337.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6355.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6411.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6412.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6426.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6427.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6433.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6441.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6448.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6457.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6464.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6472.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6476.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6479.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6505.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6509.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6516.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6519.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6542.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6543.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6547.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6552.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6570.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6573.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6577.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6616.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6626.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6637.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6661.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6681.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6707.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6711.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6714.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6715.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6726.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6730.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6738.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6744.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6773.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6775.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6778.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6782.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6807.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6824.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6826.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6828.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6851.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6864.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6881.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6887.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6897.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6914.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6939.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6949.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6963.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6989.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6992.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7006.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7010.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7032.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7042.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7055.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7060.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7068.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7072.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7079.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7095.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7097.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7098.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7108.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7114.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7115.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7117.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7130.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7143.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7146.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7154.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7175.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7185.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7201.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7211.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7223.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7226.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7228.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7231.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7256.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7287.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7290.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7313.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7341.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7356.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7379.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7384.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7408.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7410.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7419.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7420.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7429.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7439.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7447.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7450.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7478.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7490.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7502.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7517.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7522.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7525.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7532.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7534.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7547.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7550.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7566.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7567.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7573.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7578.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7594.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7607.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7612.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7641.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7645.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7663.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7675.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7686.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7698.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7700.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7720.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7734.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7745.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7760.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7765.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7779.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7783.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7812.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7824.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7825.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7828.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7856.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7863.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7864.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7866.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7884.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7886.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7915.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7919.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7926.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7939.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7951.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7955.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7983.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7999.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8016.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8018.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8019.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8038.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8043.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8061.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8064.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8075.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8079.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8082.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8094.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8103.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8117.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8128.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8132.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8142.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8148.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8162.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8183.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8202.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8214.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8217.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8228.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8251.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8252.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8267.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8272.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8278.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8281.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8286.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8293.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8307.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8314.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8318.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8320.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8339.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8351.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8352.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8356.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8359.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8369.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8374.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8378.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8381.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8384.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8387.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8405.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8417.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8421.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8423.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8435.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8443.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8447.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8462.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8463.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8468.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8479.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8485.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8494.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8507.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8508.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8513.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8516.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8534.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8537.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8538.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8550.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8564.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8568.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8577.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8578.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8580.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8582.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8599.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8616.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8631.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8637.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8651.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8655.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8657.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8695.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8697.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8699.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8711.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8727.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8730.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8733.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8746.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8747.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8760.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8762.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8777.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8783.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8792.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8795.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8805.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8838.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8855.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8897.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8904.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8910.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8939.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8945.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8962.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8975.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8980.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8983.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8985.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8988.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9003.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9019.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9031.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9034.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9040.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9042.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9076.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9081.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9123.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9141.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9151.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9152.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9154.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9162.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9164.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9189.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9191.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9201.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9208.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9214.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9216.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9228.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9248.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9258.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9273.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9284.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9307.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9320.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9348.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9366.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9379.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9393.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9395.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9399.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9403.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9410.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9416.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9426.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9429.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9432.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9461.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9489.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9490.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9495.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9498.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9521.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9537.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9555.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9558.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9605.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9609.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9619.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9620.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9630.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9642.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9664.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9667.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9693.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9724.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9732.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9736.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9750.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9756.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9774.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9775.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9776.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9797.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9806.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9815.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9819.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9825.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9830.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9839.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9845.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9848.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9864.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9883.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9891.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9893.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9897.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9910.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9918.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9922.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9935.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9943.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9951.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9966.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9969.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9978.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9981.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9994.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9998.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10005.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10025.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10027.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10062.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10086.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10087.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10090.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10094.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10104.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10108.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10109.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10117.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10124.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10128.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10146.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10149.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10152.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10156.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10166.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10168.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10171.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10183.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10185.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10197.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10201.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10205.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10207.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10210.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10218.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10228.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10238.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10240.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10241.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10253.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10267.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10282.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10288.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10329.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10345.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10381.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10388.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10410.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10415.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10419.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10422.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10433.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10439.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10442.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10446.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10450.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10466.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10469.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10490.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10497.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10522.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10547.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10548.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10550.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10558.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10566.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10567.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10584.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10586.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10590.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10593.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10608.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10626.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10634.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10639.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10644.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10662.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10673.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10680.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10684.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10708.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10728.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10742.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10756.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10760.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10794.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10795.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10797.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10810.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10818.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10825.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10826.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10828.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10844.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10845.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10863.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10868.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10881.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10897.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10904.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10942.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10957.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10959.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10981.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10999.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11001.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11004.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11014.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11025.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11038.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11041.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11050.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11076.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11102.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11114.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11124.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11129.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11138.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11152.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11180.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11199.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11205.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11215.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11216.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11220.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11229.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11238.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11241.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11251.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11255.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11258.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11264.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11272.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11286.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11290.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11313.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11322.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11338.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11345.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11357.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11358.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11379.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11389.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11399.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11403.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11420.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11421.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11428.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11441.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11467.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11468.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11472.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11473.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11476.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11504.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11546.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11556.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11568.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11582.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11594.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11604.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11605.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11610.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11618.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11625.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11632.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11644.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11651.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11656.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11683.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11696.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11722.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11736.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11737.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11762.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11764.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11788.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11808.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11809.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11815.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11819.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11821.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11828.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11830.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11841.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11850.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11856.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11876.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11881.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11887.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11891.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11893.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11902.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11903.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11909.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11931.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11938.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11964.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11968.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12007.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12011.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12026.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12044.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12065.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12098.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12124.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12130.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12134.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12184.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12189.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12209.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12230.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12245.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12261.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12263.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12282.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12297.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12305.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12315.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12323.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12328.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12335.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12338.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12346.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12354.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12355.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12363.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12370.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12374.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12386.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12392.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12395.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12410.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12412.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12420.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12432.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12435.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12439.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12461.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12470.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12476.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12499.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12519.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12532.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12536.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12537.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12547.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12549.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12569.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12586.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12593.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12603.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12605.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12608.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12611.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12624.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12628.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12641.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12644.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12653.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12655.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12698.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12706.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12717.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12723.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12773.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12775.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12781.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12783.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12792.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12829.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12845.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12854.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12861.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12863.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12870.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12877.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12879.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12894.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12901.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12902.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12917.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12970.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12981.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12983.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12999.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13052.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13054.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13061.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13066.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13076.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13100.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13103.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13104.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13107.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13114.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13120.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13159.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13169.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13172.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13176.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13185.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13186.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13214.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13216.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13229.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13247.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13264.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13272.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13277.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13294.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13308.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13314.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13316.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13322.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13328.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13336.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13354.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13357.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13360.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13385.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13388.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13390.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13409.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13415.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13420.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13421.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13495.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13508.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13513.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13523.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13550.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13558.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13561.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13576.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13578.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13611.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13613.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13629.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13663.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13664.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13666.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13682.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13695.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13706.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13713.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13731.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13733.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13737.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13738.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13742.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13743.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13763.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13779.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13786.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13809.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13810.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13824.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13830.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13844.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13846.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13857.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13894.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13902.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13913.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13942.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13960.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13966.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13970.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13971.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13972.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13977.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13982.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13989.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14001.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14003.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14023.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14031.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14043.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14060.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14061.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14072.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14081.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14094.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14100.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14101.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14129.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14135.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14160.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14175.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14177.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14186.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14192.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14196.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14235.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14236.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14255.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14262.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14270.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14273.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14284.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14290.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14337.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14339.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14350.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14360.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14363.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14382.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14416.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14424.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14431.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14441.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14451.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14464.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14484.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14487.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14504.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14508.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14515.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14521.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14551.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14559.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14565.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14590.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14617.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14655.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14657.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14661.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14665.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14670.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14677.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14705.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14716.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14741.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14756.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14759.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14775.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14793.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14820.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14823.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14829.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14847.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14857.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14861.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14864.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14877.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14883.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14900.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14901.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14902.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14922.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14942.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14951.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14954.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14964.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14972.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14987.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14988.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15001.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15016.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15034.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15036.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15050.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15057.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15074.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15080.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15087.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15090.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15119.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15127.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15140.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15141.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15143.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15159.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15171.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15174.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15186.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15188.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15197.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15202.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15228.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15255.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15257.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15280.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15289.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15292.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15311.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15335.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15340.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15346.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15348.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15353.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15369.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15380.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15382.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15385.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15391.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15403.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15405.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15413.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15427.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15453.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15509.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15519.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15537.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15544.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15550.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15562.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15576.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15581.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15587.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15595.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15614.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15615.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15621.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15637.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15641.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15642.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15663.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15666.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15699.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15703.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15708.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15723.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15724.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15743.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15755.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15770.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15772.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15789.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15795.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15811.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15816.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15834.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15838.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15848.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15852.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15861.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15866.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15892.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15896.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15904.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15908.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15909.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15910.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15955.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15960.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15962.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15964.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15966.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15983.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15990.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15996.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15999.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16010.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16013.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16031.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16041.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16052.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16054.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16056.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16065.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16067.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16069.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16072.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16095.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16096.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16117.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16121.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16131.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16148.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16167.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16192.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16200.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16203.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16211.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16212.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16213.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16218.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16220.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16227.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16233.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16267.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16272.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16279.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16304.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16307.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16319.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16324.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16327.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16341.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16350.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16351.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16361.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16376.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16398.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16404.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16412.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16430.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16445.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16448.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16470.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16495.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16517.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16528.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16529.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16538.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16544.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16549.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16550.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16556.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16559.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16565.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16577.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16584.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16588.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16591.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16607.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16608.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16612.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16624.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16631.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16632.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16638.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16639.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16647.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16664.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16665.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16670.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16681.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16691.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16696.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16697.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16740.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16748.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16761.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16771.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16772.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16773.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16784.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16786.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16813.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16816.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16817.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16818.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16833.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16840.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16848.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16852.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16856.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16864.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16874.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16904.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16906.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16910.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16942.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16956.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16958.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16966.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16969.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16971.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16972.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16992.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17014.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17022.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17026.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17052.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17064.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17069.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17073.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17074.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17077.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17080.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17083.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17089.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17115.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17132.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17136.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17160.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17161.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17162.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17165.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17186.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17192.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17212.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17215.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17227.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17246.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17261.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17264.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17272.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17273.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17293.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17314.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17316.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17345.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17347.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17352.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17356.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17367.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17374.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17376.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17401.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17406.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17407.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17411.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17412.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17415.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17417.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17426.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17460.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17474.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17479.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17481.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17497.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17507.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17521.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17530.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17567.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17580.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17581.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17598.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17605.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17613.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17614.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17624.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17625.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17645.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17646.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17652.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17656.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17664.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17672.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17674.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17700.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17714.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17716.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17721.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17731.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17732.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17733.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17736.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17743.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17744.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17748.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17767.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17770.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17772.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17775.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17781.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17807.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17812.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17815.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17829.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17878.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17900.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17906.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17907.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17909.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17913.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17914.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17920.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17926.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17927.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17929.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17935.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17956.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17968.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17988.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18011.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18016.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18018.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18021.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18022.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18058.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18068.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18075.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18090.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18093.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18104.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18127.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18146.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18149.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18163.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18186.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18211.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18215.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18220.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18229.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18231.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18235.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18252.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18259.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18269.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18322.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18327.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18336.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18352.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18379.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18394.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18400.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18404.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18406.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18417.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18441.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18442.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18446.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18467.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18496.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18509.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18523.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18546.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18556.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18560.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18578.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18584.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18586.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18599.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18614.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18641.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18647.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18657.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18663.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18677.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18679.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18693.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18698.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18699.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18703.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18706.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18726.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18729.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18731.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18734.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18751.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18757.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18760.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18762.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18769.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18774.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18784.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18785.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18793.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18797.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18800.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18801.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18818.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18825.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18830.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18846.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18849.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18850.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18894.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18939.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18942.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18945.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18946.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18950.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18952.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18975.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18979.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18993.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19010.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19032.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19051.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19053.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19056.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19061.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19078.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19080.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19086.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19093.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19097.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19145.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19163.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19173.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19183.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19192.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19196.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19199.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19215.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19220.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19224.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19231.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19237.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19250.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19290.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19293.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19304.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19313.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19314.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19331.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19341.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19342.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19346.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19358.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19360.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19361.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19368.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19371.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19398.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19412.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19413.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19415.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19416.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19438.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19453.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19460.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19471.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19472.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19474.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19478.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19485.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19488.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19496.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19503.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19504.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19519.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19520.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19523.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19542.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19554.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19559.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19560.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19582.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19592.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19599.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19604.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19632.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19639.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19642.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19643.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19652.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19665.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19666.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19668.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19669.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19680.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19684.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19721.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19726.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19736.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19757.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19770.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19771.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19775.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19790.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19806.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19810.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19820.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19822.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19830.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19832.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19838.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19875.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19901.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19906.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19911.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19939.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19950.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19970.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19977.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19999.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20033.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20041.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20073.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20091.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20092.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20096.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20098.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20107.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20138.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20147.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20157.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20158.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20185.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20247.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20249.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20260.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20262.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20267.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20288.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20289.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20290.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20305.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20346.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20350.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20353.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20354.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20357.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20359.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20379.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20380.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20381.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20393.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20412.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20415.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20416.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20425.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20434.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20435.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20442.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20460.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20468.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20478.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20504.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20516.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20540.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20585.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20591.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20592.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20608.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20618.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20620.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20624.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20643.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20654.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20670.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20674.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20702.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20711.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20713.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20714.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20724.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20725.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20734.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20789.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20798.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20819.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20825.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20826.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20827.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20844.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20848.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20855.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20858.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20860.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20871.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20882.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20883.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20891.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20892.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20899.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20904.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20906.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20912.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20913.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20931.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20972.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20974.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20991.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21015.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21032.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21051.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21058.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21064.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21070.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21075.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21077.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21084.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21099.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21118.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21168.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21170.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21174.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21186.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21188.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21214.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21215.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21222.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21226.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21230.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21232.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21253.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21255.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21269.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21281.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21296.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21302.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21304.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21318.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21329.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21344.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21345.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21354.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21357.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21363.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21385.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21390.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21424.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21444.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21494.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21495.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21510.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21515.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21538.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21546.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21551.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21552.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21555.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21566.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21590.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21598.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21611.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21618.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21646.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21649.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21651.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21656.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21678.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21686.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21698.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21706.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21707.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21709.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21727.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21731.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21741.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21751.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21755.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21763.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21778.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21779.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21795.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21803.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21811.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21815.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21830.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21838.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21854.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21898.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21902.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21925.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21962.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21981.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22005.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22017.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22018.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22021.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22026.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22030.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22031.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22033.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22039.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22042.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22046.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22050.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22053.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22066.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22092.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22095.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22097.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22103.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22119.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22123.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22130.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22136.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22151.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22159.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22172.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22186.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22191.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22216.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22218.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22221.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22223.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22241.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22254.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22260.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22263.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22267.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22293.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22297.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22304.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22307.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22308.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22309.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22318.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22342.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22349.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22366.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22373.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22385.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22388.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22389.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22398.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22411.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22417.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22420.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22436.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22464.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22469.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22476.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22487.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22498.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22500.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22513.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22528.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22544.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22548.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22561.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22577.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22588.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22626.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22630.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22635.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22669.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22684.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22698.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22702.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22705.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22706.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22710.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22712.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22720.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22725.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22750.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22761.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22784.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22789.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22805.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22808.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22814.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22826.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22833.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22855.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22875.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22877.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22891.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22904.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22908.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22910.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22920.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22922.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22925.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22927.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22929.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22938.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22950.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22954.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22977.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22992.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22993.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22998.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22999.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23003.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23006.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23007.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23018.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23024.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23037.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23095.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23103.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23110.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23128.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23130.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23156.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23162.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23178.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23195.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23200.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23206.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23213.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23216.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23237.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23248.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23263.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23264.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23271.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23272.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23282.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23285.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23293.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23308.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23378.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23385.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23388.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23398.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23403.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23404.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23412.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23424.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23439.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23443.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23447.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23451.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23467.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23480.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23498.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23506.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23507.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23517.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23539.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23547.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23575.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23583.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23590.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23591.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23594.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23605.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23630.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23637.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23638.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23644.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23647.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23653.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23668.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23681.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23682.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23697.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23702.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23703.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23709.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23712.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23718.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23728.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23738.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23740.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23747.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23762.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23769.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23785.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23791.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23805.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23815.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23841.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23855.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23864.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23874.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23884.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23896.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23907.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23914.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23917.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23927.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23939.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23946.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23954.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23955.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23958.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23968.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23977.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23993.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24000.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24001.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24007.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24008.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24014.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24041.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24043.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24048.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24066.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24096.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24107.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24123.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24128.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24130.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24139.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24181.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24185.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24188.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24190.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24198.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24204.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24234.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24242.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24252.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24261.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24267.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24271.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24272.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24277.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24278.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24280.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24281.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24296.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24310.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24327.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24330.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24331.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24335.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24377.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24393.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24400.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24415.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24422.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24429.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24431.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24453.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24463.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24469.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24471.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24472.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24478.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24487.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24532.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24535.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24539.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24548.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24574.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24576.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24584.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24595.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24597.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24608.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24609.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24614.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24627.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24633.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24646.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24649.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24663.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24674.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24677.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24687.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24713.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24721.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24722.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24732.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24741.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24769.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24770.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24773.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24784.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24788.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24800.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24807.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24821.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24827.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24829.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24883.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24884.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24908.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24919.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24932.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24946.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24955.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24971.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24974.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24980.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24989.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24998.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25007.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25009.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25011.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25012.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25013.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25060.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25061.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25098.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25100.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25110.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25111.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25148.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25165.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25169.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25173.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25184.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25191.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25214.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25217.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25229.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25253.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25258.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25264.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25269.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25285.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25286.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25290.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25294.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25305.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25307.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25310.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25327.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25332.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25335.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25351.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25374.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25381.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25390.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25413.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25414.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25428.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25487.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25505.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25509.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25521.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25543.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25549.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25567.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25572.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25582.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25585.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25599.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25618.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25625.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25634.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25637.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25654.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25669.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25683.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25691.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25707.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25751.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25776.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25795.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25806.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25810.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25823.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25827.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25831.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25832.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25848.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25852.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25900.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25921.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25924.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25927.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25931.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25946.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25953.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25955.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25958.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25964.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25981.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25986.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26006.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26007.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26010.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26023.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26024.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26028.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26033.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26056.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26068.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26073.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26081.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26115.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26155.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26183.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26186.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26217.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26232.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26242.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26243.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26248.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26261.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26264.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26265.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26275.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26276.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26295.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26300.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26346.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26348.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26350.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26355.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26362.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26374.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26380.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26417.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26419.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26422.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26435.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26450.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26469.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26492.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26496.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26512.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26534.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26535.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26564.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26572.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26595.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26601.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26622.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26629.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26636.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26647.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26657.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26659.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26679.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26680.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26683.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26686.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26720.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26721.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26726.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26761.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26795.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26797.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26807.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26811.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26819.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26820.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26832.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26833.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26834.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26839.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26846.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26850.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26863.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26870.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26871.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26876.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26888.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26895.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26906.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26927.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26934.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26949.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26962.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26968.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27011.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27014.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27018.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27038.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27041.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27042.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27050.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27051.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27052.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27083.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27100.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27118.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27127.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27128.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27135.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27136.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27148.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27169.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27174.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27187.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27206.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27234.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27241.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27272.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27281.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27288.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27298.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27306.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27313.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27314.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27328.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27342.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27343.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27345.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27354.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27370.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27377.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27378.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27407.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27421.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27426.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27427.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27448.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27469.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27473.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27476.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27482.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27485.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27491.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27498.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27501.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27508.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27510.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27519.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27524.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27528.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27540.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27543.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27552.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27554.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27558.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27566.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27601.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27607.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27616.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27639.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27649.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27651.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27668.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27682.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27709.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27714.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27721.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27724.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27727.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27733.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27736.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27746.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27776.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27797.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27807.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27828.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27841.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27849.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27879.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27885.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27897.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27925.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27940.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27949.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27975.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27990.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27992.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27998.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28001.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28002.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28022.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28032.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28037.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28055.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28097.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28132.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28147.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28168.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28189.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28201.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28202.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28204.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28218.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28221.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28238.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28240.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28269.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28271.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28274.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28276.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28283.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28286.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28303.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28344.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28363.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28376.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28379.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28380.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28387.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28415.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28421.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28424.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28463.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28480.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28494.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28508.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28515.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28519.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28558.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28581.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28599.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28604.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28615.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28627.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28654.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28658.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28665.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28670.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28677.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28681.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28682.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28695.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28732.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28736.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28741.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28747.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28752.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28756.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28788.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28806.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28815.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28821.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28826.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28834.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28841.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28844.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28848.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28856.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28861.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28866.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28872.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28874.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28878.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28915.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28926.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28934.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28956.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28970.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28973.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28989.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29025.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29028.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29031.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29042.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29047.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29061.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29066.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29112.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29129.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29135.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29136.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29148.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29151.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29157.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29164.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29167.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29177.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29184.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29187.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29192.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29198.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29221.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29236.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29260.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29280.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29303.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29306.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29318.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29319.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29332.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29339.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29349.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29352.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29356.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29357.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29363.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29368.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29374.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29384.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29411.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29419.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29420.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29423.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29434.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29442.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29444.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29447.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29453.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29483.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29507.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29508.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29534.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29559.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29561.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29569.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29573.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29577.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29598.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29599.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29610.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29611.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29626.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29627.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29629.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29633.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29641.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29653.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29660.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29664.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29674.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29679.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29685.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29694.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29701.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29718.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29735.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29740.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29744.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29752.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29753.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29775.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29784.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29802.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29803.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29804.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29813.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29815.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29818.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29819.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29829.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29833.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29865.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29894.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29899.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29906.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29953.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29959.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29968.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29980.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29992.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30018.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30019.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30026.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30028.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30037.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30041.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30055.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30074.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30089.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30099.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30117.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30119.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30139.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30141.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30151.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30159.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30160.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30161.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30170.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30172.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30176.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30186.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30200.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30214.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30218.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30247.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30271.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30281.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30282.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30313.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30316.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30318.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30323.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30331.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30348.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30350.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30351.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30353.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30368.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30373.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30385.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30409.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30414.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30416.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30419.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30446.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30453.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30469.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30482.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst43.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst95.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst203.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst228.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst232.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst245.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst379.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30489.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30490.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30500.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30511.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30528.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30530.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30544.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30555.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30560.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30585.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30586.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30593.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30602.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30603.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30607.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30611.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30612.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30621.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30658.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30664.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30670.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30674.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30690.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30694.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30699.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30719.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30731.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30732.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30737.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30742.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30747.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30756.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30777.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30785.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30792.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30819.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30829.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30834.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30845.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30849.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30855.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30862.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30875.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30881.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30895.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30899.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30901.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30902.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30910.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30918.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30953.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30957.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30959.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30965.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30971.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30980.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31005.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31017.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31053.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31060.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31066.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31074.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31076.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31081.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31087.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31094.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31095.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31099.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31100.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31104.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31112.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31135.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31139.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31171.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31186.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31213.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31220.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31231.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31241.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31242.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31248.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31273.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31283.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31297.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31298.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31302.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31305.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31322.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31338.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31341.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31343.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31350.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31363.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31396.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31400.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31410.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31417.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31446.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31452.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31464.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31470.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31483.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31485.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31486.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31508.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31513.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31521.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31524.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31528.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31545.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31550.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31554.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31555.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31579.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31590.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31596.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31608.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31614.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31615.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31634.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31666.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31668.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31674.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31675.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31676.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31701.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31705.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31714.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31721.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31737.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31746.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31757.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31773.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31785.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31812.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31817.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31823.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31829.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31848.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31850.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31853.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31862.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31869.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31883.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31892.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31896.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31899.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31907.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31946.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31949.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31952.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31954.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31955.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31969.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31972.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31975.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31978.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31989.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32000.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32001.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32002.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32009.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32013.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32024.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32026.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32041.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32048.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32093.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32095.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32104.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32116.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32119.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32144.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32149.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32156.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32185.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32190.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32195.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32196.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32200.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32204.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32205.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32215.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32231.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32234.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32238.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32257.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32272.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32303.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32309.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32347.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32356.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32357.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32358.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32391.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32396.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32407.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32411.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32437.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32439.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32442.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32452.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32461.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32469.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32470.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32474.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32476.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32478.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32491.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32495.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32498.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32502.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32516.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32524.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32554.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32586.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32593.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32604.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32607.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32634.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32661.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32668.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32674.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32682.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32708.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32709.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32736.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32741.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32770.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32772.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32784.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32787.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32791.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32797.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32813.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32817.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32820.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32839.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32853.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32861.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32869.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32875.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32877.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32878.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32881.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32897.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32901.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32914.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32922.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32935.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32936.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32955.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32972.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32973.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32978.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32985.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32989.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33013.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33038.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33073.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33089.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33115.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33125.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33128.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33135.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33151.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33155.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33159.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33174.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33254.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33264.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33273.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33284.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33285.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33302.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33312.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33320.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33324.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33335.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33338.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33342.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33355.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33359.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33363.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33368.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33370.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33378.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33389.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33398.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33404.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33405.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33413.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33421.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33433.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33479.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33500.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33503.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33528.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33540.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33546.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33547.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33550.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33552.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33559.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33565.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33584.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33595.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33596.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33603.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33607.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33609.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33616.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33627.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33655.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33676.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33697.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33704.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33715.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33741.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33760.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33828.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33838.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33850.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33861.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33874.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33881.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33896.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33897.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33906.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33913.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33942.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33944.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33951.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33952.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33961.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33963.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33973.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33978.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33990.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34001.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34002.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34006.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34013.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34025.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34042.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34052.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34057.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34066.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34069.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34086.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34094.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34111.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34158.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34160.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst14.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst21.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst22.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst34.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst37.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst40.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst43.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst48.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst49.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst55.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst60.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst61.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst62.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst71.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst73.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst79.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst81.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst83.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst100.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst149.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst157.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst158.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst162.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst186.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst196.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst220.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst237.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst243.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst247.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst249.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst250.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst255.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst266.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst275.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst283.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst295.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst303.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst311.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst328.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst338.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst348.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst350.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst353.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst374.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst376.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst390.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst396.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst451.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst454.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst498.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst500.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst535.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst549.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst550.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst554.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst568.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst581.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst587.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst591.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst602.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst613.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst616.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst617.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst641.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst642.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst652.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst686.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst696.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst703.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst704.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst712.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst718.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst720.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst731.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst736.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst774.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst776.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst789.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst814.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst824.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst828.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst833.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst838.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst842.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst847.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst849.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst850.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst857.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst863.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst871.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst875.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst880.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst885.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst889.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst892.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst899.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst905.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst929.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst959.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst961.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst43.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst95.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst203.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst228.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst232.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst245.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst379.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst970.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst990.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1001.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1006.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1008.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1042.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1043.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1046.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1054.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1059.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1060.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1061.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1064.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1068.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1077.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1083.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1091.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1105.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1110.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1142.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1146.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1148.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1151.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1164.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1166.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1169.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1172.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1174.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1188.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1191.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1193.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1199.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1210.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1212.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1226.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1231.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1232.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1238.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1239.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1245.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1246.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1256.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1261.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1291.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1294.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1297.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1302.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1329.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1331.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1332.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1334.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1338.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1362.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1373.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1375.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1376.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1393.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1394.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1398.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1403.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1416.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1419.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1430.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1434.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1435.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1445.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1451.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1453.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1457.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1465.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1487.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1498.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1519.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1520.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1521.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1536.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1539.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1543.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1554.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1562.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1566.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1567.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1570.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1572.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1579.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1580.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1600.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1611.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1620.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1629.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1633.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1646.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1657.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1703.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1710.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1716.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1727.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1730.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1738.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1739.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1741.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1754.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1767.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1772.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1777.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1785.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1802.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1805.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1818.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1849.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1850.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1854.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1860.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1862.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1879.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1892.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1895.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1896.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1898.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1905.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1916.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1921.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1923.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1932.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1946.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1951.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1952.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1961.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1979.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1984.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1988.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1993.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1995.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2000.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2010.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2033.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2075.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2084.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2096.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2106.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2111.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2123.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2136.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2137.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2140.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2141.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2144.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2147.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2160.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2174.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2176.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2199.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2210.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2217.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2220.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2225.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2231.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2243.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2250.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2280.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2288.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2303.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2306.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2307.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2317.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2343.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2345.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2346.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2348.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2358.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2362.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2364.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2367.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2368.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2383.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2399.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2419.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2446.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2461.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2466.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2472.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2479.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2481.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2492.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2494.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2503.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2507.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2510.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2533.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2543.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2551.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2554.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2561.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2590.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2597.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2632.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2637.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2649.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2656.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2662.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2669.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2688.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2698.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2711.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2713.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2723.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2728.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2731.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2755.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2761.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2764.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2794.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2797.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2813.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2845.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2849.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2858.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2861.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2881.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2907.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2912.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2913.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2946.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2959.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2988.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3013.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3031.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3041.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3046.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3062.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3067.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3078.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3095.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3116.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3122.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3133.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3154.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3159.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3170.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3190.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3196.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3209.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3214.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3218.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3238.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3295.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3298.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3299.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3303.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3306.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3308.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3322.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3329.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3339.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3360.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3367.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3371.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3380.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3387.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3391.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3395.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3405.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3427.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3436.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3439.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3449.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3462.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3465.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3475.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3488.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3498.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3501.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3513.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3524.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3525.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3528.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3536.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3540.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3544.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3575.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3582.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3595.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3610.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3612.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3613.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3616.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3618.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3626.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3638.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3639.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3641.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3650.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3660.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3661.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3671.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3679.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3692.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3693.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3694.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3700.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3702.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3713.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3716.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3718.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3730.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3736.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3738.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3743.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3758.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3768.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3769.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3780.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3784.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3798.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3800.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3803.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3809.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3831.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3851.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3854.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3855.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3856.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3865.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3866.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3876.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3884.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3889.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3902.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3904.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3918.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3944.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3953.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3954.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3969.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3977.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3982.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3997.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4011.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4012.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4019.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4027.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4039.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4041.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4043.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4046.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4051.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4055.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4056.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4073.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4078.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4096.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4105.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4107.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4112.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4115.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4118.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4122.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4140.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4160.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4168.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4170.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4172.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4175.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4189.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4202.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4215.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4221.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4268.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4269.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4273.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4279.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4285.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4286.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4294.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4297.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4304.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4349.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4354.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4360.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4373.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4376.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4377.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4378.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4381.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4382.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4383.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4392.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4422.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4426.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4430.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4446.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4450.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4459.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4461.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4467.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4485.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4489.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4506.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4521.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4523.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4526.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4541.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4602.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4609.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4610.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4620.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4626.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4631.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4634.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4650.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4658.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4672.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4676.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4689.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4745.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4767.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4771.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4774.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4798.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4817.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4821.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4826.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4829.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4845.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4864.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4866.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4883.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4884.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4886.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4888.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4889.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4891.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4898.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4899.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4905.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4915.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4923.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4932.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4955.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4956.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4974.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4976.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4977.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4980.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4990.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5001.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5007.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5012.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5023.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5050.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5051.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5056.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5061.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5073.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5080.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5099.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5107.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5134.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5140.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5143.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5145.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5146.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5161.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5171.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5196.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5205.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5211.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5219.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5226.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5270.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5284.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5314.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5316.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5322.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5337.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5359.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5364.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5368.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5370.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5384.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5392.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5405.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5409.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5422.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5427.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5434.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5437.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5444.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5446.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5455.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5470.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5471.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5474.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5479.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5489.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5497.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5499.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5509.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5524.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5547.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5553.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5560.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5567.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5585.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5590.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5591.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5598.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5601.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5611.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5622.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5627.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5657.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5667.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5684.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5698.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5704.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5707.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5709.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5715.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5735.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5741.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5747.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5758.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5759.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5761.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5773.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5774.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5785.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5790.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5799.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5813.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5814.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5853.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5886.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5894.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5896.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5913.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5923.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5924.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5931.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5950.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5956.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5959.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5966.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5967.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5974.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5976.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5981.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5992.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6000.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6009.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6016.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6018.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6032.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6044.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6070.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6108.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6118.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6120.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6128.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6130.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6176.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6181.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6189.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6198.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6201.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6209.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6213.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6234.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6236.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6247.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6266.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6286.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6310.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6312.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6314.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6318.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6325.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6327.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6343.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6346.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6370.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6376.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6380.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6395.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6403.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6411.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6415.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6427.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6435.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6439.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6443.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6447.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6456.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6462.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6463.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6485.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6511.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6514.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6522.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6524.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6528.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6535.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6539.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6568.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6591.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6603.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6609.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6617.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6630.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6634.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6655.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6665.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6674.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6676.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6677.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6682.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6684.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6697.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6703.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6714.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6727.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6742.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6748.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6761.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6778.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6782.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6801.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6817.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6820.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6828.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6832.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6862.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6866.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6879.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6914.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6925.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6939.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6940.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6945.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6946.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6950.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6962.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6975.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6981.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6993.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7014.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7016.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7017.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7062.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7079.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7097.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7098.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7100.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7102.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7109.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7115.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7116.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7117.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7119.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7127.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7130.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7132.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7136.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7158.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7164.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7168.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7186.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7197.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7205.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7206.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7208.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7211.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7217.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7226.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7227.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7238.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7254.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7272.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7283.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7291.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7292.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7297.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7306.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7312.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7317.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7319.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7340.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7356.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7365.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7387.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7392.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7481.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7488.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7490.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7491.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7496.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7509.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7536.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7539.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7547.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7553.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7579.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7583.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7592.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7598.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7649.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7653.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7672.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7675.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7678.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7680.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7682.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7688.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7733.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7740.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7744.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7760.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7770.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7776.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7777.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7781.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7790.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7793.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7798.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7799.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7801.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7804.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7816.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7833.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7837.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7849.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7852.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7855.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7856.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7867.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7877.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7915.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7918.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7921.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7926.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7931.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7938.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7941.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7948.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7958.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7982.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7986.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7988.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8021.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8022.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8025.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8042.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8044.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8050.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8054.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8056.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8078.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8089.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8091.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8110.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8112.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8117.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8120.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8133.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8156.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8159.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8163.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8179.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8180.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8199.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8204.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8218.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8234.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8241.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8249.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8251.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8263.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8277.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8282.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8290.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8292.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8309.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8315.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8337.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8344.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8349.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8361.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8386.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8399.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8402.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8416.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8420.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8421.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8448.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8465.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8467.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8473.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8484.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8489.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8497.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8503.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8507.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8519.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8534.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8536.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8542.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8543.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8551.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8568.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8569.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8581.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8585.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8586.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8592.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8594.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8605.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8613.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8623.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8624.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8639.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8646.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8659.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8680.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8689.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8719.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8724.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8754.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8756.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8761.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8789.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8791.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8797.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8826.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8848.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8882.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8889.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8895.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8896.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8941.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8945.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8949.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8962.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8968.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8973.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8980.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8984.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9002.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9006.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9011.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9018.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9019.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9025.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9039.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9060.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9062.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9080.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9091.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9092.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9093.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9101.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9104.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9108.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9129.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9136.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9148.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9154.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9163.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9164.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9172.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9178.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9191.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9196.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9200.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9221.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9230.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9258.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9266.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9289.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9301.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9302.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9356.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9358.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9360.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9362.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9388.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9400.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9403.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9412.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9421.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9424.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9425.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9431.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9433.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9443.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9444.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9447.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9451.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9494.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9512.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9516.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9517.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9520.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9536.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9546.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9552.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9556.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9563.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9593.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9602.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9618.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9634.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9639.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9674.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9675.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9677.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9683.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9699.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9713.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9715.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9716.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9725.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9734.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9739.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9775.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9783.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9788.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9790.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9794.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9801.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9806.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9807.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9818.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9822.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9840.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9847.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9849.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9878.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9891.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9903.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9911.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9915.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9917.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9927.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9929.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9936.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9945.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9953.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9974.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9998.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10003.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10005.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10006.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10020.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10022.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10027.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10047.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10064.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10081.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10085.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10089.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10102.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10109.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10111.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10112.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10152.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10156.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10164.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10196.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10211.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10217.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10233.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10246.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10260.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10270.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10296.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10305.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10308.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10321.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10323.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10330.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10339.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10341.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10344.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10345.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10360.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10369.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10372.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10385.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10400.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10406.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10411.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10415.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10417.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10433.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10436.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10445.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10471.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10472.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10474.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10475.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10479.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10495.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10501.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10509.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10514.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10527.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10548.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10552.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10561.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10563.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10570.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10586.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10590.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10595.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10605.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10607.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10614.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10616.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10619.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10645.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10666.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10672.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10691.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10696.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10713.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10716.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10729.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10731.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10734.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10744.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10752.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10762.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10773.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10774.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10777.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10783.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10794.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10806.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10810.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10814.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10816.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10817.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10818.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10848.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10862.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10863.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10866.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10905.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10934.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10976.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10977.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10988.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10996.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10998.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11003.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11012.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11014.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11015.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11022.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11040.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11041.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11063.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11066.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11069.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11070.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11076.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11080.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11086.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11107.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11109.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11119.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11137.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11176.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11187.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11225.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11242.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11252.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11305.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11310.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11316.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11324.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11326.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11340.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11351.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11352.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11361.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11381.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11397.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11398.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11413.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11423.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11426.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11429.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11430.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11432.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11441.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11444.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11446.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11460.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11463.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11468.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11469.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11470.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11471.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11489.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11490.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11500.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11542.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11557.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11577.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11584.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11589.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11593.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11595.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11596.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11603.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11605.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11607.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11612.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11613.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11615.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11630.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11632.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11664.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11675.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11684.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11705.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11706.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11714.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11722.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11736.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11770.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11775.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11776.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11815.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11823.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11828.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11834.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11846.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11854.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11860.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11874.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11942.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11943.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11952.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11957.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11962.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11971.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11978.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11997.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11998.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12003.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12005.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12012.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12026.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12040.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12057.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12081.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12083.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12084.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12092.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12098.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12106.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12118.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12123.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12142.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12184.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12197.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12212.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12213.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12215.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12235.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12248.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12259.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12262.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12263.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12271.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12305.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12313.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12343.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst14.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst21.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst22.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst34.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst37.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst40.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst43.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst48.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst49.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst55.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst60.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst61.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst62.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst71.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst73.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst79.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst81.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst83.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst100.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst149.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst157.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst158.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst162.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst186.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst196.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst220.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst237.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst243.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst247.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst249.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst250.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst255.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst266.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst275.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst283.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst295.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst303.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst311.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst328.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst338.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst348.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst350.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst353.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst374.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst376.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst390.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst396.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst451.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst454.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst498.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst500.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst535.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst549.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst550.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst554.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst568.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst581.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst587.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst591.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst602.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst613.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst616.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst617.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst641.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst642.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst652.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst686.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst696.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst703.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst704.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst712.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst718.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst720.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst731.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst736.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst774.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst776.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst789.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst814.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst824.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst828.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst833.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst838.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst842.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst847.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst849.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst850.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst857.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst863.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst871.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst875.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst880.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst885.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst889.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst892.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst899.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst905.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst929.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst959.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst961.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst43.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst95.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst203.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst228.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst232.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst245.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst379.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst970.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst990.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1001.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1006.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1008.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1042.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1043.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1046.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1054.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1059.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1060.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1061.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1064.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1068.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1077.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1083.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1091.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1105.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1110.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1142.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1146.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1148.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1151.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1164.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1166.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1169.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1172.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1174.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1188.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1191.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1193.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1199.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1210.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1212.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1226.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1231.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1232.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1238.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1239.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1245.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1246.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1256.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1261.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1291.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1294.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1297.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1302.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1329.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1331.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1332.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1334.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1338.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1362.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1373.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1375.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1376.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1393.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1394.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1398.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1403.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1416.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1419.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1430.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1434.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1435.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1445.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1451.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1453.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1457.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1465.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1487.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1498.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1520.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1521.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1536.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1539.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1543.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1554.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1562.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1566.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1567.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1570.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1572.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1579.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1580.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1600.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1611.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1620.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1629.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1633.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1646.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1657.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1703.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1710.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1716.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1727.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1730.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1738.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1739.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1741.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1754.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1767.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1772.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1777.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1785.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1802.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1805.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1818.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1849.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1850.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1854.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1860.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1862.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1879.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1892.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1895.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1896.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1898.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1905.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1916.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1921.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1923.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1932.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1946.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1951.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1952.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1961.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1979.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1984.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1988.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1993.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1995.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2000.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2010.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2033.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2075.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2084.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2096.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2106.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2111.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2123.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2136.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2137.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2140.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2141.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2144.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2147.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2160.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2174.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2176.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2199.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2210.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2217.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2220.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2225.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2231.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2243.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2250.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2280.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2288.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2303.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2306.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2307.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2317.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2343.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2345.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2346.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2348.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2358.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2362.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2364.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2367.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2368.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2383.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2399.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2419.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2446.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2461.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2466.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2472.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2479.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2481.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2492.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2494.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2503.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2507.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2510.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2533.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2543.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2551.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2554.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2561.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2590.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2597.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2632.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2637.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2649.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2656.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2662.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2669.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2688.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2698.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2711.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2713.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2723.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2728.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2731.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2755.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2761.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2764.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2794.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2797.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2813.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2845.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2849.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2858.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2861.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2881.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2907.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2912.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2913.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2946.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2959.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2988.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3013.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3031.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3041.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3046.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3062.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3067.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3078.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3095.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3116.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3122.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3133.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3154.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3159.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3170.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3190.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3196.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3209.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3214.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3218.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3238.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3295.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3298.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3299.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3303.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3306.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3308.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3322.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3329.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3339.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3360.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3367.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3371.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3380.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3387.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3391.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3405.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3427.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3436.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3439.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3449.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3462.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3465.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3488.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3498.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3501.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3513.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3524.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3525.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3528.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3536.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3540.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3544.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3575.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3582.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3595.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3610.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3612.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3613.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3616.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3618.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3626.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3638.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3639.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3641.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3650.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3660.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3661.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3671.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3679.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3692.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3693.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3694.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3700.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3702.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3713.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3716.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3718.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3730.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3736.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3738.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3743.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3758.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3768.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3769.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3780.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3784.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3798.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3800.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3803.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3809.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3831.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3851.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3854.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3855.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3856.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3865.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3866.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3876.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3884.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3889.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3902.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3904.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3918.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3944.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3953.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3954.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3969.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3977.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3982.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3997.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4011.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4012.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4019.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4027.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4039.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4041.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4043.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4046.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4051.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4055.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4056.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4073.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4078.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4096.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4105.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4107.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4112.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4115.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4118.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4122.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4140.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4160.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4168.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4170.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4172.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4175.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4189.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4202.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4215.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4221.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4268.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4269.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4273.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4279.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4285.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4286.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4294.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4297.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4304.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4349.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4354.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4360.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4373.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4376.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4377.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4378.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4381.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4382.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4383.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4392.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4422.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4426.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4430.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4446.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4450.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4459.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4461.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4467.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4485.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4489.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4506.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4521.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4523.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4526.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4541.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4602.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4609.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4610.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4620.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4626.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4631.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4634.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4650.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4658.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4672.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4676.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4689.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4745.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4767.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4771.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4774.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4798.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4817.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4821.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4826.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4829.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4845.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4864.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4866.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4883.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4884.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4886.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4888.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4889.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4891.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4898.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4899.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4905.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4923.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4932.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4955.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4956.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4974.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4976.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4977.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4980.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4990.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5001.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5007.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5012.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5023.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5050.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5051.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5056.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5061.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5073.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5080.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5099.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5107.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5134.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5140.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5143.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5145.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5146.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5161.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5171.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5196.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5205.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5211.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5219.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5226.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5270.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5284.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5314.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5316.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5322.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5337.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5359.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5364.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5368.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5370.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5384.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5392.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5405.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5409.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5422.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5427.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5434.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5437.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5444.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5446.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5455.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5470.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5471.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5474.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5479.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5489.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5497.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5499.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5509.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5524.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5547.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5553.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5560.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5567.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5585.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5590.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5591.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5598.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5601.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5611.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5622.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5627.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5657.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5667.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5684.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5698.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5704.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5707.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5709.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5715.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5741.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5747.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5758.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5759.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5761.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5773.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5774.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5785.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5790.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5799.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5813.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5814.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5853.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5886.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5894.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5896.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5913.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5923.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5924.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5931.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5950.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5956.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5959.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5966.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5967.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5974.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5976.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5981.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5992.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6000.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6009.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6016.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6018.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6032.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6044.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6070.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6108.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6118.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6120.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6128.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6130.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6176.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6181.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6189.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6198.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6201.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6209.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6213.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6234.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6236.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6247.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6266.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6286.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6310.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6312.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6314.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6318.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6325.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6327.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6343.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6346.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6370.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6376.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6380.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6395.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6403.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6411.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6415.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6427.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6435.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6439.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6443.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6447.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6456.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6462.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6463.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6485.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6511.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6514.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6522.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6524.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6528.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6535.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6539.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6568.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6591.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6603.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6609.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6617.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6630.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6634.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6655.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6665.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6674.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6676.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6677.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6682.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6684.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6697.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6703.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6714.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6727.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6742.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6748.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6761.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6778.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6782.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6801.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6817.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6820.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6828.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6832.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6862.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6866.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6879.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6914.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6925.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6939.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6940.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6945.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6946.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6950.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6962.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6975.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6981.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6993.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7014.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7016.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7017.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7062.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7079.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7097.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7098.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7100.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7102.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7109.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7115.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7116.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7117.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7119.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7127.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7130.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7132.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7136.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7158.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7164.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7168.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7186.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7197.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7205.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7206.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7208.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7211.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7217.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7226.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7227.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7238.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7254.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7272.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7283.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7291.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7292.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7297.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7306.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7312.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7317.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7319.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7340.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7343.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7356.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7365.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7387.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7392.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7481.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7488.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7490.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7491.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7496.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7509.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7536.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7539.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7547.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7553.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7579.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7583.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7592.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7598.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7649.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7653.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7672.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7675.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7678.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7680.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7682.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7688.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7733.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7740.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7744.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7760.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7770.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7776.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7777.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7781.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7790.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7793.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7798.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7799.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7801.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7804.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7816.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7833.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7837.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7849.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7852.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7855.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7856.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7867.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7877.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7915.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7918.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7921.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7926.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7931.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7938.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7941.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7948.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7958.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7982.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7986.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7988.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8021.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8022.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8025.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8042.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8044.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8050.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8054.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8056.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8078.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8089.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8091.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8110.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8112.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8117.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8120.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8133.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8156.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8159.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8163.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8179.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8180.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8199.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8204.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8218.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8234.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8241.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8249.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8251.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8263.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8277.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8282.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8290.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8292.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8309.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8315.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8337.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8344.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8349.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8361.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8386.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8399.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8402.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8416.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8420.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8421.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8448.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8459.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8465.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8467.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8473.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8484.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8489.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8497.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8503.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8507.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8519.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8534.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8536.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8542.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8543.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8551.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8568.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8569.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8581.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8585.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8586.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8592.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8594.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8605.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8613.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8623.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8624.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8639.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8646.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8659.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8680.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8689.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8719.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8724.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8754.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8756.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8761.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8789.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8791.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8797.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8826.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8848.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8882.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8889.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8895.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8896.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8941.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8945.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8949.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8962.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8968.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8973.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8980.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8984.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9002.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9006.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9011.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9018.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9019.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9025.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9039.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9060.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9062.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9080.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9091.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9092.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9093.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9101.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9104.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9108.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9129.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9136.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9148.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9154.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9163.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9164.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9172.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9178.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9191.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9196.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9200.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9221.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9230.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9258.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9266.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9289.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9302.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9356.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9358.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9360.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9362.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9388.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9400.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9403.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9412.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9421.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9424.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9425.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9431.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9433.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9443.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9444.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9447.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9451.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9494.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9512.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9516.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9517.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9520.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9536.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9546.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9552.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9556.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9563.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9593.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9602.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9618.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9634.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9639.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9674.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9675.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9677.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9683.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9699.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9713.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9715.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9716.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9725.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9734.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9739.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9775.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9783.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9788.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9790.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9794.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9801.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9806.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9807.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9818.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9822.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9840.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9847.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9849.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9878.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9891.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9903.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9911.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9915.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9917.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9927.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9929.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9936.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9945.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9953.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9974.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9998.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10003.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10005.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10006.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10020.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10022.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10027.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10047.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10064.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10081.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10089.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10102.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10109.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10111.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10112.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10138.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10152.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10156.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10164.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10196.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10211.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10217.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10233.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10246.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10260.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10270.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10296.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10305.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10308.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10321.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10323.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10330.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10339.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10341.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10344.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10345.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10360.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10369.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10372.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10385.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10400.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10406.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10411.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10415.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10417.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10433.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10436.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10445.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10471.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10472.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10474.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10475.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10479.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10495.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10501.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10509.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10514.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10527.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10548.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10552.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10561.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10563.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10570.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10586.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10590.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10595.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10605.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10607.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10614.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10616.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10619.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10645.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10666.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10672.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10691.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10696.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10713.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10716.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10729.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10731.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10734.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10744.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10752.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10762.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10773.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10774.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10777.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10783.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10794.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10806.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10810.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10814.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10816.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10817.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10818.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10848.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10862.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10863.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10866.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10905.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10934.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10976.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10977.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10988.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10996.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10998.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11003.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11012.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11014.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11015.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11022.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11040.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11041.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11063.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11066.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11069.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11070.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11076.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11080.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11086.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11107.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11109.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11119.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11137.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11176.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11187.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11225.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11242.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11252.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11305.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11310.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11316.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11324.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11326.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11340.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11351.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11352.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11361.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11381.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11398.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11413.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11423.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11426.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11429.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11430.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11432.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11441.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11444.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11446.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11460.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11463.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11468.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11469.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11470.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11471.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11489.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11490.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11500.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11542.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11557.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11577.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11584.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11589.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11593.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11595.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11596.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11603.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11605.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11607.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11612.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11613.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11615.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11630.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11632.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11664.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11675.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11684.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11705.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11706.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11714.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11722.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11736.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11770.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11775.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11776.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11815.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11823.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11828.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11834.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11846.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11854.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11860.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11874.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11942.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11943.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11952.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11957.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11962.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11971.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11978.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11997.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11998.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12003.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12005.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12012.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12026.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12040.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12057.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12081.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12083.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12084.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12092.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12098.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12106.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12118.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12123.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12142.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12184.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12197.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12212.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12213.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12215.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12235.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12248.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12259.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12262.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12263.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12271.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12305.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12313.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12343.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst14.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst21.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst22.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst34.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst37.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst40.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst43.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst48.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst49.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst55.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst60.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst61.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst62.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst71.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst73.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst79.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst81.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst83.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst100.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst149.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst157.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst158.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst162.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst186.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst196.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst220.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst237.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst243.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst247.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst249.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst250.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst255.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst266.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst275.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst283.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst295.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst303.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst311.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst328.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst338.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst348.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst350.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst353.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst374.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst376.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst390.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst396.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst451.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst454.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst498.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst500.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst535.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst549.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst550.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst554.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst568.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst581.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst587.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst591.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst602.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst613.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst616.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst617.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst641.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst642.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst652.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst686.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst696.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst703.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst704.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst712.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst718.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst720.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst731.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst736.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst774.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst776.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst789.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst814.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst824.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst828.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst833.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst838.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst842.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst847.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst849.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst850.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst857.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst863.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst871.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst875.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst880.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst885.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst889.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst892.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst899.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst905.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst929.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst959.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst961.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst43.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst95.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst203.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst228.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst232.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst245.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst379.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst970.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst990.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1001.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1006.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1008.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1042.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1043.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1046.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1054.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1059.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1060.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1061.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1064.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1068.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1077.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1083.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1091.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1105.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1110.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1142.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1146.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1148.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1151.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1164.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1166.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1169.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1172.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1174.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1188.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1191.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1193.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1199.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1210.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1212.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1226.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1231.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1232.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1238.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1239.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1245.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1246.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1256.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1261.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1291.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1294.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1297.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1302.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1329.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1331.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1332.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1334.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1338.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1362.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1373.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1375.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1376.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1393.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1394.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1398.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1403.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1416.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1419.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1430.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1434.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1435.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1445.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1451.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1453.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1457.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1465.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1487.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1498.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1520.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1521.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1536.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1539.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1543.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1554.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1562.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1566.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1567.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1570.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1572.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1579.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1580.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1600.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1611.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1620.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1629.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1633.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1646.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1657.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1703.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1710.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1716.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1727.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1730.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1738.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1739.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1741.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1754.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1767.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1772.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1777.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1785.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1802.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1805.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1818.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1849.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1850.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1854.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1860.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1862.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1879.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1892.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1895.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1896.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1898.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1905.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1916.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1921.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1923.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1932.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1946.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1951.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1952.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1961.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1979.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1984.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1988.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1993.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1995.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2000.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2010.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2033.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2075.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2084.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2096.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2106.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2111.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2123.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2136.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2137.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2140.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2141.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2144.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2147.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2160.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2174.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2176.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2199.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2210.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2217.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2220.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2225.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2231.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2243.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2250.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2280.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2288.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2303.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2306.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2307.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2317.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2343.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2345.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2346.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2348.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2358.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2362.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2364.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2367.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2368.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2383.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2399.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2419.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2446.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2461.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2466.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2472.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2479.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2481.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2492.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2494.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2503.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2507.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2510.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2533.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2543.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2551.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2554.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2561.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2590.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2597.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2632.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2637.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2649.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2656.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2662.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2669.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2688.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2698.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2711.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2713.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2723.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2728.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2731.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2755.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2761.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2764.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2794.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2797.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2813.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2845.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2849.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2858.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2861.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2881.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2907.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2912.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2913.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2946.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2959.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2988.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3013.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3031.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3041.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3046.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3062.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3067.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3078.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3095.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3116.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3122.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3133.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3154.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3159.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3170.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3190.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3196.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3209.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3214.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3218.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3238.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3295.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3298.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3299.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3303.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3306.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3308.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3322.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3329.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3339.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3360.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3367.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3371.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3380.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3387.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3391.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3405.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3427.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3436.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3439.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3449.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3462.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3465.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3488.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3498.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3501.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3513.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3524.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3525.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3528.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3536.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3540.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3544.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3575.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3582.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3595.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3610.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3612.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3613.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3616.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3618.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3626.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3638.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3639.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3641.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3650.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3660.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3661.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3671.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3679.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3692.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3693.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3694.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3700.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3702.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3713.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3716.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3718.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3730.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3736.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3738.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3743.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3758.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3768.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3769.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3780.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3784.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3798.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3800.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3803.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3809.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3831.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3851.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3854.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3855.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3856.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3865.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3866.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3876.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3884.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3889.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3902.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3904.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3918.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3944.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3953.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3954.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3969.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3977.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3982.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3997.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4011.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4012.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4019.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4027.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4039.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4041.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4043.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4046.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4051.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4055.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4056.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4073.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4078.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4096.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4105.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4107.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4112.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4115.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4118.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4122.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4140.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4160.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4168.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4170.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4172.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4175.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4189.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4202.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4215.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4221.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4268.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4269.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4273.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4279.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4285.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4286.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4294.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4297.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4304.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4349.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4354.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4360.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4373.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4376.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4377.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4378.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4381.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4382.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4383.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4392.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4422.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4426.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4430.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4446.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4450.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4459.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4461.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4467.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4485.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4489.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4506.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4521.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4523.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4526.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4541.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4602.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4609.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4610.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4620.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4626.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4631.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4634.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4650.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4658.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4672.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4676.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4689.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4745.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4767.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4771.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4774.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4798.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4817.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4821.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4826.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4829.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4845.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4864.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4866.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4883.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4884.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4886.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4888.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4889.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4891.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4898.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4899.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4905.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4923.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4932.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4955.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4956.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4974.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4976.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4977.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4980.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4990.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5001.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5007.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5012.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5023.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5050.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5051.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5056.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5061.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5073.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5080.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5099.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5107.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5134.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5140.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5143.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5145.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5146.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5161.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5171.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5196.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5205.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5211.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5219.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5226.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5270.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5284.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5314.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5316.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5322.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5337.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5359.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5364.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5368.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5370.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5384.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5392.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5405.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5409.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5422.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5427.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5434.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5437.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5444.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5446.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5455.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5470.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5471.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5474.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5479.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5489.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5497.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5499.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5509.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5524.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5547.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5553.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5560.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5567.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5585.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5590.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5591.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5598.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5601.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5611.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5622.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5627.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5657.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5667.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5684.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5698.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5704.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5707.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5709.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5715.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5741.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5747.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5758.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5759.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5761.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5773.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5774.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5785.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5790.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5799.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5813.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5814.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5853.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5886.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5894.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5896.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5913.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5923.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5924.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5931.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5950.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5956.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5959.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5966.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5967.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5974.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5976.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5981.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5992.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6000.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6009.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6016.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6018.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6032.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6044.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6070.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6108.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6118.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6120.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6128.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6130.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6176.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6181.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6189.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6198.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6201.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6209.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6213.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6234.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6236.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6247.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6266.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6286.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6310.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6312.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6314.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6318.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6325.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6327.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6343.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6346.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6370.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6376.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6380.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6395.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6403.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6411.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6415.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6427.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6435.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6439.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6443.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6447.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6456.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6462.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6463.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6485.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6511.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6514.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6522.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6524.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6528.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6535.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6539.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6568.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6591.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6603.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6609.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6617.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6630.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6634.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6655.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6665.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6674.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6676.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6677.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6682.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6684.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6697.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6703.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6714.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6727.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6742.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6748.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6761.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6778.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6782.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6801.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6817.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6820.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6828.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6832.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6862.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6866.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6879.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6914.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6925.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6939.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6940.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6945.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6946.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6950.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6962.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6975.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6981.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6993.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7014.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7016.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7017.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7062.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7079.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7097.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7098.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7100.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7102.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7109.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7115.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7116.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7117.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7119.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7127.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7130.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7132.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7136.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7158.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7164.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7168.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7186.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7197.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7205.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7206.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7208.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7211.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7217.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7226.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7227.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7238.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7254.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7272.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7283.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7291.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7292.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7297.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7306.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7312.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7317.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7319.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7340.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7343.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7356.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7365.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7387.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7392.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7481.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7488.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7490.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7491.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7496.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7509.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7536.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7539.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7547.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7553.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7579.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7583.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7592.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7598.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7649.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7653.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7672.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7675.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7678.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7680.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7682.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7688.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7733.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7740.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7744.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7760.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7770.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7776.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7777.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7781.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7790.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7793.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7798.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7799.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7801.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7804.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7816.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7833.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7837.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7849.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7852.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7855.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7856.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7867.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7877.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7915.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7918.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7921.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7926.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7931.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7938.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7941.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7948.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7958.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7982.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7986.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7988.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8021.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8022.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8025.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8042.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8044.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8050.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8054.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8056.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8078.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8089.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8091.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8110.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8112.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8117.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8120.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8133.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8156.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8159.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8163.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8179.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8180.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8199.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8204.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8218.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8234.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8241.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8249.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8251.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8263.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8277.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8282.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8290.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8292.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8309.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8315.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8337.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8344.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8349.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8361.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8386.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8399.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8402.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8416.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8420.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8421.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8448.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8459.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8465.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8467.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8473.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8484.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8489.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8497.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8503.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8507.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8519.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8534.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8536.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8542.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8543.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8551.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8568.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8569.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8581.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8585.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8586.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8592.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8594.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8605.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8613.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8623.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8624.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8639.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8646.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8659.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8680.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8689.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8719.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8724.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8754.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8756.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8761.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8789.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8791.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8797.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8826.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8848.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8882.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8889.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8895.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8896.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8941.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8945.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8949.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8962.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8968.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8973.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8980.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8984.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9002.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9006.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9011.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9018.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9019.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9025.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9039.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9060.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9062.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9080.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9091.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9092.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9093.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9101.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9104.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9108.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9129.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9136.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9148.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9154.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9163.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9164.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9172.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9178.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9191.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9196.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9200.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9221.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9230.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9258.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9266.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9289.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9302.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9356.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9358.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9360.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9362.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9388.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9400.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9403.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9412.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9421.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9424.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9425.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9431.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9433.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9443.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9444.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9447.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9451.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9494.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9512.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9516.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9517.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9520.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9536.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9546.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9552.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9556.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9563.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9593.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9602.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9618.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9634.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9639.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9674.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9675.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9677.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9683.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9699.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9713.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9715.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9716.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9725.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9734.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9739.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9775.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9783.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9788.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9790.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9794.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9801.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9806.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9807.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9818.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9822.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9840.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9847.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9849.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9878.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9891.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9903.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9911.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9915.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9917.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9927.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9929.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9936.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9945.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9953.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9974.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9998.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10003.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10005.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10006.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10020.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10022.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10027.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10047.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10064.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10081.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10089.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10102.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10109.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10111.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10112.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10138.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10152.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10156.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10164.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10196.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10211.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10217.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10233.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10246.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10260.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10270.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10296.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10305.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10308.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10321.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10323.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10330.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10339.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10341.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10344.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10345.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10360.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10369.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10372.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10385.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10400.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10406.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10411.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10415.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10417.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10433.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10436.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10445.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10471.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10472.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10474.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10475.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10479.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10495.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10501.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10509.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10514.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10527.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10548.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10552.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10561.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10563.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10570.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10586.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10590.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10595.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10605.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10607.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10614.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10616.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10619.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10645.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10666.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10672.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10691.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10696.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10713.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10716.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10729.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10731.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10734.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10744.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10752.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10762.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10773.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10774.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10777.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10783.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10794.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10806.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10810.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10814.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10816.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10817.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10818.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10848.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10862.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10863.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10866.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10905.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10934.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10976.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10977.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10988.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10996.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10998.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11003.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11012.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11014.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11015.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11022.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11040.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11041.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11063.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11066.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11069.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11070.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11076.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11080.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11086.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11107.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11109.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11119.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11137.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11176.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11187.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11225.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11242.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11252.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11305.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11310.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11316.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11324.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11326.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11340.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11351.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11352.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11361.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11381.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11398.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11413.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11423.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11426.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11429.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11430.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11432.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11441.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11444.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11446.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11460.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11463.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11468.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11469.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11470.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11471.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11489.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11490.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11500.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11542.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11557.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11577.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11584.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11589.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11593.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11595.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11596.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11603.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11605.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11607.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11612.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11613.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11615.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11630.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11632.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11664.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11675.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11684.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11705.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11706.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11714.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11722.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11736.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11770.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11775.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11776.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11815.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11823.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11828.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11834.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11846.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11854.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11860.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11874.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11942.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11943.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11952.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11957.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11962.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11971.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11978.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11997.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11998.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12003.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12005.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12012.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12026.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12040.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12057.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12081.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12083.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12084.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12092.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12098.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12106.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12118.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12123.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12142.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12184.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12197.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12212.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12213.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12215.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12235.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12248.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12259.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12262.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12263.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12271.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12305.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12313.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12343.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst14.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst21.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst22.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst34.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst37.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst40.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst43.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst48.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst49.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst55.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst60.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst61.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst62.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst71.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst73.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst79.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst81.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst83.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst100.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst149.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst157.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst158.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst162.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst186.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst196.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst220.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst237.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst243.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst247.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst249.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst250.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst255.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst266.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst275.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst283.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst295.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst303.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst311.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst328.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst338.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst348.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst350.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst353.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst374.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst376.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst390.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst396.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst451.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst454.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst498.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst500.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst535.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst549.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst550.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst554.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst568.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst581.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst587.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst591.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst602.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst613.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst616.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst617.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst641.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst642.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst652.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst686.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst696.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst703.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst704.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst712.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst718.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst720.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst731.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst736.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst774.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst776.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst789.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst814.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst824.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst828.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst833.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst838.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst842.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst847.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst849.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst850.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst857.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst863.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst871.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst875.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst880.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst885.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst889.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst892.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst899.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst905.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst929.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst959.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst961.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst43.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst95.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst203.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst228.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst232.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst245.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst379.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst970.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst990.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1001.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1006.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1008.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1042.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1043.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1046.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1054.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1059.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1060.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1061.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1064.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1068.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1077.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1083.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1091.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1105.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1110.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1142.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1146.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1148.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1151.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1164.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1166.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1169.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1172.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1174.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1188.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1191.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1193.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1199.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1210.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1212.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1226.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1231.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1232.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1238.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1239.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1245.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1246.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1256.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1261.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1291.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1294.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1297.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1302.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1329.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1331.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1332.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1334.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1338.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1362.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1373.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1375.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1376.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1393.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1394.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1398.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1403.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1416.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1419.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1430.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1434.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1435.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1445.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1451.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1453.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1457.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1465.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1487.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1498.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1520.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1521.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1536.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1539.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1543.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1554.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1562.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1566.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1567.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1570.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1572.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1579.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1580.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1600.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1611.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1620.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1629.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1633.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1646.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1657.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1703.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1710.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1716.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1727.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1730.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1738.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1739.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1741.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1754.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1767.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1772.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1777.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1785.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1802.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1805.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1818.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1849.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1850.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1854.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1860.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1862.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1879.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1892.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1895.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1896.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1898.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1905.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1916.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1921.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1923.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1932.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1946.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1951.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1952.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1961.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1979.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1984.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1988.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1993.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1995.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2000.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2010.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2033.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2075.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2084.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2096.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2106.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2111.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2123.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2136.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2137.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2140.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2141.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2144.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2147.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2160.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2174.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2176.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2199.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2210.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2217.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2220.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2225.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2231.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2243.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2250.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2280.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2288.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2303.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2306.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2307.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2317.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2343.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2345.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2346.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2348.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2358.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2362.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2364.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2367.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2368.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2383.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2399.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2419.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2446.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2461.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2466.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2472.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2479.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2481.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2492.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2494.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2503.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2507.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2510.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2533.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2543.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2551.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2554.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2561.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2590.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2597.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2632.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2637.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2649.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2656.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2662.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2669.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2688.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2698.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2711.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2713.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2723.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2728.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2731.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2755.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2761.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2764.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2794.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2797.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2813.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2845.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2849.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2858.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2861.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2881.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2907.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2912.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2913.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2946.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2959.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2988.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3013.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3031.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3041.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3046.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3062.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3067.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3078.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3095.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3116.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3122.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3133.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3154.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3159.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3170.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3190.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3196.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3209.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3214.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3218.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3238.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3295.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3298.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3299.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3303.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3306.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3308.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3322.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3329.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3339.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3360.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3367.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3371.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3380.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3387.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3391.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3405.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3427.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3436.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3439.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3449.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3462.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3465.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3488.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3498.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3501.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3513.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3524.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3525.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3528.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3536.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3540.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3544.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3575.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3582.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3595.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3610.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3612.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3613.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3616.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3618.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3626.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3638.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3639.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3641.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3650.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3660.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3661.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3671.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3679.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3692.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3693.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3694.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3700.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3702.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3713.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3716.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3718.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3730.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3736.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3738.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3743.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3758.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3768.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3769.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3780.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3784.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3798.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3800.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3803.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3809.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3831.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3851.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3854.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3855.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3856.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3865.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3866.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3876.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3884.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3889.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3902.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3904.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3918.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3944.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3953.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3954.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3969.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3977.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3982.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3997.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4011.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4012.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4019.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4027.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4039.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4041.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4043.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4046.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4051.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4055.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4056.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4073.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4078.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4096.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4105.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4107.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4112.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4115.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4118.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4122.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4140.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4160.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4168.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4170.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4172.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4175.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4189.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4202.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4215.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4221.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4268.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4269.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4273.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4279.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4285.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4286.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4294.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4297.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4304.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4349.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4354.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4360.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4373.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4376.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4377.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4378.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4381.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4382.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4383.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4392.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4422.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4426.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4430.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4446.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4450.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4459.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4461.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4467.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4485.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4489.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4506.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4521.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4523.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4526.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4541.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4602.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4609.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4610.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4620.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4626.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4631.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4634.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4650.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4658.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4672.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4676.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4689.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4745.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4767.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4771.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4774.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4798.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4817.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4821.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4826.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4829.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4845.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4864.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4866.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4883.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4884.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4886.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4888.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4889.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4891.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4898.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4899.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4905.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4923.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4932.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4955.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4956.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4974.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4976.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4977.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4980.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4990.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5001.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5007.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5012.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5023.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5050.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5051.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5056.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5061.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5073.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5080.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5099.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5107.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5134.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5140.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5143.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5145.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5146.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5161.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5171.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5196.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5205.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5211.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5219.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5226.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5270.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5284.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5314.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5316.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5322.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5337.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5359.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5364.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5368.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5370.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5384.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5392.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5405.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5409.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5422.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5427.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5434.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5437.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5444.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5446.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5455.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5470.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5471.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5474.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5479.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5489.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5497.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5499.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5509.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5524.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5547.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5553.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5560.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5567.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5585.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5590.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5591.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5598.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5601.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5611.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5622.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5627.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5657.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5667.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5684.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5698.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5704.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5707.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5709.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5715.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5741.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5747.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5758.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5759.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5761.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5773.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5774.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5785.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5790.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5799.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5813.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5814.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5853.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5886.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5894.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5896.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5913.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5923.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5924.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5931.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5950.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5956.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5959.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5966.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5967.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5974.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5976.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5981.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5992.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6000.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6009.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6016.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6018.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6032.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6044.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6070.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6108.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6118.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6120.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6128.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6130.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6176.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6181.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6189.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6198.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6201.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6209.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6213.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6234.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6236.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6247.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6266.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6286.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6310.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6312.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6314.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6318.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6325.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6327.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6343.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6346.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6370.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6376.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6380.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6395.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6403.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6411.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6415.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6427.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6435.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6439.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6443.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6447.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6456.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6462.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6463.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6485.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6511.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6514.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6522.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6524.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6528.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6535.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6539.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6568.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6591.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6603.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6609.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6617.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6630.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6634.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6655.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6665.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6674.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6676.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6677.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6682.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6684.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6697.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6703.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6714.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6727.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6742.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6748.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6761.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6778.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6782.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6801.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6817.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6820.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6828.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6832.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6862.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6866.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6879.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6914.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6925.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6939.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6940.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6945.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6946.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6950.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6962.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6975.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6981.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6993.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7014.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7016.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7017.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7062.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7079.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7097.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7098.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7100.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7102.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7109.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7115.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7116.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7117.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7119.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7127.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7130.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7132.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7136.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7158.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7164.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7168.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7186.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7197.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7205.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7206.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7208.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7211.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7217.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7226.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7227.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7238.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7254.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7272.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7283.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7291.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7292.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7297.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7306.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7312.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7317.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7319.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7340.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7343.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7356.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7365.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7387.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7392.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7481.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7488.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7490.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7491.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7496.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7509.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7536.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7539.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7547.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7553.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7579.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7583.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7592.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7598.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7649.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7653.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7672.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7675.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7678.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7680.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7682.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7688.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7733.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7740.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7744.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7760.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7770.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7776.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7777.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7781.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7790.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7793.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7798.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7799.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7801.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7804.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7816.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7833.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7837.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7849.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7852.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7855.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7856.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7867.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7877.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7915.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7918.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7921.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7926.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7931.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7938.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7941.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7948.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7958.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7982.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7986.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7988.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8021.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8022.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8025.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8042.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8044.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8050.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8054.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8056.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8078.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8089.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8091.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8110.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8112.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8117.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8120.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8133.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8156.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8159.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8163.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8179.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8180.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8199.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8204.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8218.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8234.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8241.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8249.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8251.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8263.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8277.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8282.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8290.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8292.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8309.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8315.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8337.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8344.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8349.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8361.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8386.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8399.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8402.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8416.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8420.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8421.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8448.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8459.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8465.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8467.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8473.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8484.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8489.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8497.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8503.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8507.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8519.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8534.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8536.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8542.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8543.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8551.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8568.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8569.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8581.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8585.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8586.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8592.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8594.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8605.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8613.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8623.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8624.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8639.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8646.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8659.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8680.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8689.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8719.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8724.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8754.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8756.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8761.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8789.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8791.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8797.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8826.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8848.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8882.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8889.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8895.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8896.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8941.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8945.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8949.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8962.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8968.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8973.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8980.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8984.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9002.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9006.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9011.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9018.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9019.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9025.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9039.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9060.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9062.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9080.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9091.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9092.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9093.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9101.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9104.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9108.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9129.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9136.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9148.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9154.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9163.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9164.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9172.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9178.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9191.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9196.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9200.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9221.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9230.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9258.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9266.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9289.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9302.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9356.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9358.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9360.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9362.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9388.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9400.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9403.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9412.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9421.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9424.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9425.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9431.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9433.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9443.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9444.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9447.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9451.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9494.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9512.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9516.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9517.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9520.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9536.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9546.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9552.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9556.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9563.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9593.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9602.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9618.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9634.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9639.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9674.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9675.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9677.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9683.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9699.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9713.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9715.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9716.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9725.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9734.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9739.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9775.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9783.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9788.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9790.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9794.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9801.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9806.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9807.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9818.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9822.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9840.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9847.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9849.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9878.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9891.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9903.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9911.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9915.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9917.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9927.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9929.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9936.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9945.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9953.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9974.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9998.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10003.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10005.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10006.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10020.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10022.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10027.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10047.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10064.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10081.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10089.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10102.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10109.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10111.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10112.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10138.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10152.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10156.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10164.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10196.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10211.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10217.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10233.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10246.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10260.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10270.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10296.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10305.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10308.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10321.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10323.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10330.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10339.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10341.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10344.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10345.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10360.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10369.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10372.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10385.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10400.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10406.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10411.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10415.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10417.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10433.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10436.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10445.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10471.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10472.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10474.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10475.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10479.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10495.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10501.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10509.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10514.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10527.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10548.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10552.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10561.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10563.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10570.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10586.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10590.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10595.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10605.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10607.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10614.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10616.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10619.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10645.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10666.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10672.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10691.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10696.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10713.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10716.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10729.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10731.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10734.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10744.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10752.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10762.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10773.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10774.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10777.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10783.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10794.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10806.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10810.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10814.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10816.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10817.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10818.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10848.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10862.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10863.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10866.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10905.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10934.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10976.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10977.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10988.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10996.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10998.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11003.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11012.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11014.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11015.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11022.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11040.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11041.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11063.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11066.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11069.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11070.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11076.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11080.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11086.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11107.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11109.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11119.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11137.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11176.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11187.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11225.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11242.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11252.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11305.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11310.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11316.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11324.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11326.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11340.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11351.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11352.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11361.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11381.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11398.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11413.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11423.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11426.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11429.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11430.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11432.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11441.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11444.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11446.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11460.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11463.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11468.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11469.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11470.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11471.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11489.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11490.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11500.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11542.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11557.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11577.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11584.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11589.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11593.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11595.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11596.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11603.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11605.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11607.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11612.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11613.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11615.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11630.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11632.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11664.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11675.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11684.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11705.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11706.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11714.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11722.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11736.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11770.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11775.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11776.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11815.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11823.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11828.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11834.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11846.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11854.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11860.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11874.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11942.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11943.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11952.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11957.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11962.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11971.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11978.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11997.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11998.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12003.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12005.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12012.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12026.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12040.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12057.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12081.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12083.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12084.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12092.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12098.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12106.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12118.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12123.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12142.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12184.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12197.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12212.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12213.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12215.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12235.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12248.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12259.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12262.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12263.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12271.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12305.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12313.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12343.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst14.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst21.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst22.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst34.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst37.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst40.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst43.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst48.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst49.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst55.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst60.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst61.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst62.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst71.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst73.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst79.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst81.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst83.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst100.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst149.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst157.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst158.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst162.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst186.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst196.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst220.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst237.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst243.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst247.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst249.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst250.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst255.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst266.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst275.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst283.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst295.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst303.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst311.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst328.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst338.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst348.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst350.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst353.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst374.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst376.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst390.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst396.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst451.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst454.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst498.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst500.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst535.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst549.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst550.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst554.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst568.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst581.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst587.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst591.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst602.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst613.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst616.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst617.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst641.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst642.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst652.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst686.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst696.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst703.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst704.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst712.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst718.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst720.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst731.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst736.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst774.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst776.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst789.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst814.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst824.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst828.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst833.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst838.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst842.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst847.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst849.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst850.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst857.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst863.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst871.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst875.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst880.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst885.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst889.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst892.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst899.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst905.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst929.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst959.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst961.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst43.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst95.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst203.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst228.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst232.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst245.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst379.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst970.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst990.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1001.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1006.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1008.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1042.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1043.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1046.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1054.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1059.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1060.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1061.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1064.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1068.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1077.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1083.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1091.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1105.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1110.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1142.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1146.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1148.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1151.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1164.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1166.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1169.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1172.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1174.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1188.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1191.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1193.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1199.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1210.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1212.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1226.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1231.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1232.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1238.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1239.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1245.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1246.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1256.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1261.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1291.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1294.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1297.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1302.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1329.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1331.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1332.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1334.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1338.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1362.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1373.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1375.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1376.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1393.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1394.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1398.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1403.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1416.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1419.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1430.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1434.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1435.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1445.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1451.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1453.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1457.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1465.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1487.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1498.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1520.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1521.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1536.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1539.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1543.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1554.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1562.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1566.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1567.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1570.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1572.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1579.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1580.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1600.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1611.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1620.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1629.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1633.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1646.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1657.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1703.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1710.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1716.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1727.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1730.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1738.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1739.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1741.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1754.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1767.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1772.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1777.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1785.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1802.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1805.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1818.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1849.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1850.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1854.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1860.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1862.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1879.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1892.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1895.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1896.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1898.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1905.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1916.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1921.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1923.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1932.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1946.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1951.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1952.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1961.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1979.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1984.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1988.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1993.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1995.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2000.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2010.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2033.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2075.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2084.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2096.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2106.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2111.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2123.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2136.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2137.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2140.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2141.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2144.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2147.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2160.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2174.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2176.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2199.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2210.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2217.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2220.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2225.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2231.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2243.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2250.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2280.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2288.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2303.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2306.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2307.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2317.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2343.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2345.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2346.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2348.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2358.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2362.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2364.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2367.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2368.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2383.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2399.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2419.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2446.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2461.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2466.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2472.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2479.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2481.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2492.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2494.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2503.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2507.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2510.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2533.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2543.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2551.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2554.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2561.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2590.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2597.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2632.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2637.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2649.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2656.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2662.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2669.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2688.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2698.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2711.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2713.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2723.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2728.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2731.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2755.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2761.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2764.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2794.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2797.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2813.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2845.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2849.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2858.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2861.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2881.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2907.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2912.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2913.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2946.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2959.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2988.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3013.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3031.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3041.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3046.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3062.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3067.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3078.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3095.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3116.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3122.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3133.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3154.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3159.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3170.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3190.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3196.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3209.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3214.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3218.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3238.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3295.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3298.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3299.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3303.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3306.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3308.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3322.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3329.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3339.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3360.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3367.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3371.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3380.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3387.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3391.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3405.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3427.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3436.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3439.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3449.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3462.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3465.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3488.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3498.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3501.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3513.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3524.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3525.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3528.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3536.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3540.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3544.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3575.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3582.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3595.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3610.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3612.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3613.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3616.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3618.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3626.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3638.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3639.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3641.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3650.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3660.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3661.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3671.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3679.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3692.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3693.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3694.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3700.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3702.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3713.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3716.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3718.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3730.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3736.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3738.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3743.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3758.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3768.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3769.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3780.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3784.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3798.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3800.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3803.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3809.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3831.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3851.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3854.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3855.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3856.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3865.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3866.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3876.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3884.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3889.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3902.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3904.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3918.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3944.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3953.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3954.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3969.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3977.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3982.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3997.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4011.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4012.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4019.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4027.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4039.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4041.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4043.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4046.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4051.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4055.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4056.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4073.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4078.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4096.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4105.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4107.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4112.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4115.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4118.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4122.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4140.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4160.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4168.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4170.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4172.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4175.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4189.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4202.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4215.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4221.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4268.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4269.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4273.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4279.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4285.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4286.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4294.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4297.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4304.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4349.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4354.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4360.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4373.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4376.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4377.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4378.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4381.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4382.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4383.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4392.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4422.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4426.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4430.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4446.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4450.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4459.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4461.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4467.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4485.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4489.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4506.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4521.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4523.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4526.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4541.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4602.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4609.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4610.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4620.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4626.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4631.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4634.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4650.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4658.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4672.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4676.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4689.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4745.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4767.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4771.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4774.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4798.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4817.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4821.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4826.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4829.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4845.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4864.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4866.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4883.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4884.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4886.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4888.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4889.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4891.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4898.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4899.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4905.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4923.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4932.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4955.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4956.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4974.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4976.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4977.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4980.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4990.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5001.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5007.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5012.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5023.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5050.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5051.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5056.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5061.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5073.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5080.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5099.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5107.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5134.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5140.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5143.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5145.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5146.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5161.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5171.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5196.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5205.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5211.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5219.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5226.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5270.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5284.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5314.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5316.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5322.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5337.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5359.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5364.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5368.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5370.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5384.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5392.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5405.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5409.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5422.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5427.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5434.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5437.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5444.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5446.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5455.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5470.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5471.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5474.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5479.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5489.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5497.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5499.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5509.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5524.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5547.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5553.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5560.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5567.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5585.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5590.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5591.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5598.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5601.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5611.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5622.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5627.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5657.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5667.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5684.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5698.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5704.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5707.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5709.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5715.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5741.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5747.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5758.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5759.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5761.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5773.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5774.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5785.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5790.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5799.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5813.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5814.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5853.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5886.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5894.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5896.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5913.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5923.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5924.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5931.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5950.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5956.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5959.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5966.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5967.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5974.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5976.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5981.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5992.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6000.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6009.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6016.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6018.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6032.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6044.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6070.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6108.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6118.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6120.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6128.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6130.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6176.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6181.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6189.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6198.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6201.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6209.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6213.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6234.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6236.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6247.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6266.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6286.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6310.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6312.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6314.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6318.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6325.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6327.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6343.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6346.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6370.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6376.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6380.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6395.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6403.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6411.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6415.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6427.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6435.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6439.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6443.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6447.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6456.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6462.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6463.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6485.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6511.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6514.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6522.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6524.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6528.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6535.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6539.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6568.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6591.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6603.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6609.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6617.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6630.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6634.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6655.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6665.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6674.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6676.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6677.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6682.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6684.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6697.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6703.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6714.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6727.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6742.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6748.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6761.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6778.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6782.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6801.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6817.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6820.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6828.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6832.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6862.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6866.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6879.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6914.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6925.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6939.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6940.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6945.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6946.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6950.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6962.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6975.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6981.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6993.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7014.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7016.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7017.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7062.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7079.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7097.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7098.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7100.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7102.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7109.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7115.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7116.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7117.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7119.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7127.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7130.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7132.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7136.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7158.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7164.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7168.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7186.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7197.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7205.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7206.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7208.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7211.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7217.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7226.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7227.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7238.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7254.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7272.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7283.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7291.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7292.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7297.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7306.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7312.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7317.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7319.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7340.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7343.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7356.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7365.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7387.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7392.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7481.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7488.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7490.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7491.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7496.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7509.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7536.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7539.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7547.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7553.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7579.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7583.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7592.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7598.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7649.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7653.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7672.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7675.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7678.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7680.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7682.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7688.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7733.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7740.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7744.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7760.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7770.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7776.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7777.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7781.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7790.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7793.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7798.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7799.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7801.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7804.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7816.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7833.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7837.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7849.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7852.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7855.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7856.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7867.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7877.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7915.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7918.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7921.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7926.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7931.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7938.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7941.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7948.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7958.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7982.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7986.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7988.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8021.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8022.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8025.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8042.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8044.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8050.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8054.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8056.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8078.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8089.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8091.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8110.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8112.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8117.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8120.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8133.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8156.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8159.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8163.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8179.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8180.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8199.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8204.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8218.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8234.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8241.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8249.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8251.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8263.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8277.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8282.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8290.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8292.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8309.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8315.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8337.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8344.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8349.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8361.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8386.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8399.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8402.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8416.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8420.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8421.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8448.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8459.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8465.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8467.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8473.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8484.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8489.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8497.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8503.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8507.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8519.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8534.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8536.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8542.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8543.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8551.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8568.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8569.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8581.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8585.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8586.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8592.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8594.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8605.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8613.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8623.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8624.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8639.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8646.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8659.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8680.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8689.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8719.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8724.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8754.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8756.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8761.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8789.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8791.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8797.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8826.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8848.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8882.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8889.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8895.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8896.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8941.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8945.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8949.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8962.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8968.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8973.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8980.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8984.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9002.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9006.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9011.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9018.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9019.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9025.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9039.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9060.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9062.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9080.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9091.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9092.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9093.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9101.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9104.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9108.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9129.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9136.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9148.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9154.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9163.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9164.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9172.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9178.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9191.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9196.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9200.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9221.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9230.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9258.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9266.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9289.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9302.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9356.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9358.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9360.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9362.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9388.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9400.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9403.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9412.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9421.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9424.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9425.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9431.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9433.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9443.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9444.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9447.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9451.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9494.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9512.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9516.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9517.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9520.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9536.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9546.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9552.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9556.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9563.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9593.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9602.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9618.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9634.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9639.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9674.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9675.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9677.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9683.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9699.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9713.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9715.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9716.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9725.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9734.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9739.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9775.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9783.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9788.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9790.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9794.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9801.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9806.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9807.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9818.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9822.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9840.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9847.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9849.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9878.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9891.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9903.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9911.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9915.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9917.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9927.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9929.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9936.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9945.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9953.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9974.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9998.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10003.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10005.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10006.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10020.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10022.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10027.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10047.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10064.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10081.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10089.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10102.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10109.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10111.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10112.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10138.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10152.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10156.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10164.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10196.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10211.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10217.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10233.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10246.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10260.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10270.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10296.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10305.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10308.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10321.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10323.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10330.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10339.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10341.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10344.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10345.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10360.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10369.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10372.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10385.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10400.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10406.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10411.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10415.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10417.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10433.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10436.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10445.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10471.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10472.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10474.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10475.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10479.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10495.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10501.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10509.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10514.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10527.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10548.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10552.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10561.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10563.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10570.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10586.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10590.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10595.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10605.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10607.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10614.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10616.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10619.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10645.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10666.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10672.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10691.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10696.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10713.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10716.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10729.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10731.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10734.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10744.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10752.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10762.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10773.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10774.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10777.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10783.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10794.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10806.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10810.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10814.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10816.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10817.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10818.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10848.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10862.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10863.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10866.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10905.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10934.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10976.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10977.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10988.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10996.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10998.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11003.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11012.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11014.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11015.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11022.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11040.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11041.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11063.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11066.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11069.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11070.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11076.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11080.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11086.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11107.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11109.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11119.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11137.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11176.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11187.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11225.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11242.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11252.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11305.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11310.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11316.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11324.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11326.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11340.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11351.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11352.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11361.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11381.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11398.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11413.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11423.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11426.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11429.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11430.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11432.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11441.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11444.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11446.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11460.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11463.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11468.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11469.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11470.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11471.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11489.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11490.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11500.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11542.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11557.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11577.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11584.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11589.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11593.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11595.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11596.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11603.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11605.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11607.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11612.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11613.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11615.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11630.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11632.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11664.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11675.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11684.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11705.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11706.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11714.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11722.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11736.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11770.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11775.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11776.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11815.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11823.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11828.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11834.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11846.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11854.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11860.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11874.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11942.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11943.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11952.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11957.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11962.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11971.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11978.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11997.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11998.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12003.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12005.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12012.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12026.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12040.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12057.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12081.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12083.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12084.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12092.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12098.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12106.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12118.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12123.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12142.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12184.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12197.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12212.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12213.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12215.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12235.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12248.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12259.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12262.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12263.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12271.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12305.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12313.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12343.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst14.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst21.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst22.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst34.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst37.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst40.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst43.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst48.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst49.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst55.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst60.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst61.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst62.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst71.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst73.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst79.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst81.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst83.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst100.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst149.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst157.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst158.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst162.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst186.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst196.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst220.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst237.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst243.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst247.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst249.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst250.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst255.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst266.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst275.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst283.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst295.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst303.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst311.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst328.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst338.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst348.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst350.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst353.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst374.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst376.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst390.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst396.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst451.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst454.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst498.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst500.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst535.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst549.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst550.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst554.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst568.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst581.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst587.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst591.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst602.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst613.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst616.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst617.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst641.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst642.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst652.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst686.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst696.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst703.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst704.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst712.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst718.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst720.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst731.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst736.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst774.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst776.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst789.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst814.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst824.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst828.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst833.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst838.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst842.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst847.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst849.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst850.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst857.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst863.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst871.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst875.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst880.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst885.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst889.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst892.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst899.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst905.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst929.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst959.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst961.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst43.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst95.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst203.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst228.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst232.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst245.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst379.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst970.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst990.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1001.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1006.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1008.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1042.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1043.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1046.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1054.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1059.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1060.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1061.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1064.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1068.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1077.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1083.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1091.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1105.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1110.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1142.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1146.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1148.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1151.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1164.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1166.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1169.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1172.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1174.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1188.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1191.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1193.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1199.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1210.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1212.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1226.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1231.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1232.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1238.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1239.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1245.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1246.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1256.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1261.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1291.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1294.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1297.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1302.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1329.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1331.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1332.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1334.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1338.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1362.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1373.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1375.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1376.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1393.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1394.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1398.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1403.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1416.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1419.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1430.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1434.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1435.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1445.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1451.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1453.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1457.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1465.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1487.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1498.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1520.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1521.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1536.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1539.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1543.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1554.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1562.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1566.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1567.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1570.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1572.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1579.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1580.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1600.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1611.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1620.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1629.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1633.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1646.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1657.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1703.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1710.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1716.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1727.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1730.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1738.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1739.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1741.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1754.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1767.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1772.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1777.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1785.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1802.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1805.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1818.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1849.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1850.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1854.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1860.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1862.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1879.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1892.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1895.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1896.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1898.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1905.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1916.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1921.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1923.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1932.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1946.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1951.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1952.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1961.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1979.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1984.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1988.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1993.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1995.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2000.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2010.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2033.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2075.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2084.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2096.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2106.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2111.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2123.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2136.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2137.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2140.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2141.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2144.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2147.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2160.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2174.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2176.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2199.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2210.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2217.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2220.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2225.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2231.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2243.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2250.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2280.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2288.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2303.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2306.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2307.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2317.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2343.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2345.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2346.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2348.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2358.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2362.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2364.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2367.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2368.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2383.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2399.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2419.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2446.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2461.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2466.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2472.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2479.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2481.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2492.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2494.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2503.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2507.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2510.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2533.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2543.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2551.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2554.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2561.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2590.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2597.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2632.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2637.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2649.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2656.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2662.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2669.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2688.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2698.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2711.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2713.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2723.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2728.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2731.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2755.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2761.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2764.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2794.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2797.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2813.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2845.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2849.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2858.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2861.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2881.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2907.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2912.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2913.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2946.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2959.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2988.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3013.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3031.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3041.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3046.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3062.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3067.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3078.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3095.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3116.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3122.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3133.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3154.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3159.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3170.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3190.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3196.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3209.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3214.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3218.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3238.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3295.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3298.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3299.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3303.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3306.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3308.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3322.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3329.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3339.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3360.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3367.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3371.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3380.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3387.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3391.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3405.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3427.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3436.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3439.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3449.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3462.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3465.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3488.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3498.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3501.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3513.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3524.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3525.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3528.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3536.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3540.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3544.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3575.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3582.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3595.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3610.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3612.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3613.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3616.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3618.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3626.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3638.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3639.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3641.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3650.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3660.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3661.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3671.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3679.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3692.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3693.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3694.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3700.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3702.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3713.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3716.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3718.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3730.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3736.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3738.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3743.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3758.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3768.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3769.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3780.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3784.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3798.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3800.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3803.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3809.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3831.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3851.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3854.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3855.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3856.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3865.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3866.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3876.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3884.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3889.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3902.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3904.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3918.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3944.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3953.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3954.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3969.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3977.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3982.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3997.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4011.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4012.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4019.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4027.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4039.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4041.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4043.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4046.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4051.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4055.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4056.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4073.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4078.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4096.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4105.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4107.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4112.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4115.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4118.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4122.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4140.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4160.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4168.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4170.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4172.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4175.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4189.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4202.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4215.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4221.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4268.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4269.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4273.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4279.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4285.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4286.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4294.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4297.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4304.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4349.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4354.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4360.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4373.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4376.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4377.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4378.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4381.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4382.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4383.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4392.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4422.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4426.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4430.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4446.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4450.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4459.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4461.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4467.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4485.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4489.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4506.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4521.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4523.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4526.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4541.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4602.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4609.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4610.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4620.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4626.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4631.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4634.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4650.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4658.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4672.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4676.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4689.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4745.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4767.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4771.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4774.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4798.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4817.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4821.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4826.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4829.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4845.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4864.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4866.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4883.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4884.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4886.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4888.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4889.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4891.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4898.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4899.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4905.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4923.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4932.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4955.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4956.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4974.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4976.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4977.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4980.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4990.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5001.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5007.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5012.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5023.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5050.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5051.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5056.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5061.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5073.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5080.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5099.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5107.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5134.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5140.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5143.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5145.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5146.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5161.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5171.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5196.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5205.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5211.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5219.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5226.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5270.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5284.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5314.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5316.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5322.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5337.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5359.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5364.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5368.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5370.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5384.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5392.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5405.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5409.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5422.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5427.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5434.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5437.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5444.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5446.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5455.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5470.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5471.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5474.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5479.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5489.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5497.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5499.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5509.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5524.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5547.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5553.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5560.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5567.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5585.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5590.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5591.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5598.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5601.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5611.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5622.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5627.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5657.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5667.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5684.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5698.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5704.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5707.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5709.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5715.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5741.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5747.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5758.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5759.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5761.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5773.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5774.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5785.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5790.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5799.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5813.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5814.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5853.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5886.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5894.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5896.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5913.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5923.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5924.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5931.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5950.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5956.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5959.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5966.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5967.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5974.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5976.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5981.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5992.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6000.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6009.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6016.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6018.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6032.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6044.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6070.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6108.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6118.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6120.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6128.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6130.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6176.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6181.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6189.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6198.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6201.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6209.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6213.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6234.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6236.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6247.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6266.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6286.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6310.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6312.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6314.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6318.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6325.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6327.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6343.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6346.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6370.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6376.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6380.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6395.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6403.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6411.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6415.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6427.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6435.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6439.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6443.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6447.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6456.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6462.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6463.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6485.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6511.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6514.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6522.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6524.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6528.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6535.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6539.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6568.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6591.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6603.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6609.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6617.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6630.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6634.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6655.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6665.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6674.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6676.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6677.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6682.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6684.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6697.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6703.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6714.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6727.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6742.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6748.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6761.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6778.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6782.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6801.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6817.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6820.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6828.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6832.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6862.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6866.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6879.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6914.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6925.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6939.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6940.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6945.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6946.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6950.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6962.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6975.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6981.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6993.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7014.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7016.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7017.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7062.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7079.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7097.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7098.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7100.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7102.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7109.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7115.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7116.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7117.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7119.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7127.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7130.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7132.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7136.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7158.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7164.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7168.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7186.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7197.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7205.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7206.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7208.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7211.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7217.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7226.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7227.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7238.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7254.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7272.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7283.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7291.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7292.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7297.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7306.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7312.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7317.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7319.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7340.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7343.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7356.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7365.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7387.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7392.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7481.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7488.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7490.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7491.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7496.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7509.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7536.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7539.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7547.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7553.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7579.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7583.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7592.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7598.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7649.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7653.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7672.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7675.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7678.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7680.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7682.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7688.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7733.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7740.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7744.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7760.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7770.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7776.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7777.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7781.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7790.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7793.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7798.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7799.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7801.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7804.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7816.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7833.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7837.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7849.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7852.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7855.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7856.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7867.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7877.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7915.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7918.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7921.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7926.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7931.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7938.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7941.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7948.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7958.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7982.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7986.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7988.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8021.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8022.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8025.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8042.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8044.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8050.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8054.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8056.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8078.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8089.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8091.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8110.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8112.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8117.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8120.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8133.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8156.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8159.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8163.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8179.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8180.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8199.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8204.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8218.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8234.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8241.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8249.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8251.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8263.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8277.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8282.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8290.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8292.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8309.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8315.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8337.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8344.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8349.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8361.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8386.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8399.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8402.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8416.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8420.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8421.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8448.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8459.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8465.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8467.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8473.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8484.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8489.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8497.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8503.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8507.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8519.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8534.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8536.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8542.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8543.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8551.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8568.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8569.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8581.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8585.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8586.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8592.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8594.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8605.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8613.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8623.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8624.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8639.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8646.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8659.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8680.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8689.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8719.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8724.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8754.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8756.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8761.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8789.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8791.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8797.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8826.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8848.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8882.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8889.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8895.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8896.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8941.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8945.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8949.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8962.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8968.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8973.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8980.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8984.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9002.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9006.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9011.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9018.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9019.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9025.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9039.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9060.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9062.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9080.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9091.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9092.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9093.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9101.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9104.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9108.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9129.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9136.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9148.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9154.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9163.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9164.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9172.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9178.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9191.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9196.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9200.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9221.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9230.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9258.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9266.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9289.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9302.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9356.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9358.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9360.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9362.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9388.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9400.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9403.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9412.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9421.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9424.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9425.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9431.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9433.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9443.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9444.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9447.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9451.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9494.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9512.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9516.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9517.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9520.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9536.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9546.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9552.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9556.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9563.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9593.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9602.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9618.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9634.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9639.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9674.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9675.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9677.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9683.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9699.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9713.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9715.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9716.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9725.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9734.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9739.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9775.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9783.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9788.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9790.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9794.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9801.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9806.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9807.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9818.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9822.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9840.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9847.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9849.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9878.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9891.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9903.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9911.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9915.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9917.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9927.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9929.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9936.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9945.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9953.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9974.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9998.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10003.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10005.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10006.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10020.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10022.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10027.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10047.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10064.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10081.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10089.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10102.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10109.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10111.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10112.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10138.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10152.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10156.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10164.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10196.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10211.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10217.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10233.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10246.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10260.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10270.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10296.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10305.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10308.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10321.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10323.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10330.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10339.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10341.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10344.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10345.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10360.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10369.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10372.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10385.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10400.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10406.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10411.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10415.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10417.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10433.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10436.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10445.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10471.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10472.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10474.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10475.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10479.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10495.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10501.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10509.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10514.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10527.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10548.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10552.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10561.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10563.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10570.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10586.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10590.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10595.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10605.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10607.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10614.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10616.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10619.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10645.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10666.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10672.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10691.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10696.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10713.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10716.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10729.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10731.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10734.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10744.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10752.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10762.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10773.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10774.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10777.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10783.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10794.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10806.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10810.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10814.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10816.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10817.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10818.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10848.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10862.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10863.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10866.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10905.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10934.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10976.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10977.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10988.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10996.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10998.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11003.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11012.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11014.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11015.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11022.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11040.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11041.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11063.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11066.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11069.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11070.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11076.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11080.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11086.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11107.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11109.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11119.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11137.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11176.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11187.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11225.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11242.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11252.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11305.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11310.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11316.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11324.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11326.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11340.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11351.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11352.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11361.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11381.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11398.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11413.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11423.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11426.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11429.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11430.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11432.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11441.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11444.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11446.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11460.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11463.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11468.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11469.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11470.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11471.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11489.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11490.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11500.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11542.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11557.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11577.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11584.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11589.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11593.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11595.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11596.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11603.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11605.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11607.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11612.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11613.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11615.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11630.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11632.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11664.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11675.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11684.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11705.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11706.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11714.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11722.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11736.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11770.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11775.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11776.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11815.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11823.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11828.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11834.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11846.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11854.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11860.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11874.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11942.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11943.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11952.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11957.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11962.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11971.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11978.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11997.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11998.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12003.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12005.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12012.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12026.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12040.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12057.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12081.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12083.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12084.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12092.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12098.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12106.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12118.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12123.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12142.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12184.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12197.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12212.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12213.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12215.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12235.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12248.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12259.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12262.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12263.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12271.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12305.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12313.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12343.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst14.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst21.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst22.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst34.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst37.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst40.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst43.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst48.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst49.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst55.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst60.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst61.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst62.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst71.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst73.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst79.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst81.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst83.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst100.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst149.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst157.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst158.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst162.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst186.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst196.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst220.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst237.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst243.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst247.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst249.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst250.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst255.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst266.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst275.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst283.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst295.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst303.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst311.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst328.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst338.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst348.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst350.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst353.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst374.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst376.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst390.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst396.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst451.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst454.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst498.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst500.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst535.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst549.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst550.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst554.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst568.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst581.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst587.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst591.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst602.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst613.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst616.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst617.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst641.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst642.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst652.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst686.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst696.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst703.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst704.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst712.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst718.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst720.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst731.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst736.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst774.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst776.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst789.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst814.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst824.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst828.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst833.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst838.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst842.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst847.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst849.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst850.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst857.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst863.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst871.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst875.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst880.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst885.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst889.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst892.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst899.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst905.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst929.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst959.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst961.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst43.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst95.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst203.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst228.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst232.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst245.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst379.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst970.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst990.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1001.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1006.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1008.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1042.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1043.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1046.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1054.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1059.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1060.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1061.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1064.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1068.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1077.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1083.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1091.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1105.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1110.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1142.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1146.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1148.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1151.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1164.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1166.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1169.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1172.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1174.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1188.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1191.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1193.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1199.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1210.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1212.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1226.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1231.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1232.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1238.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1239.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1245.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1246.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1256.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1261.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1291.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1294.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1297.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1302.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1329.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1331.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1332.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1334.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1338.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1362.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1373.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1375.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1376.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1393.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1394.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1398.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1403.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1416.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1419.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1430.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1434.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1435.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1445.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1451.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1453.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1457.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1465.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1487.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1498.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1520.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1521.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1536.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1539.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1543.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1554.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1562.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1566.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1567.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1570.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1572.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1579.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1580.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1600.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1611.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1620.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1629.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1633.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1646.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1657.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1703.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1710.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1716.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1727.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1730.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1738.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1739.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1741.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1754.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1767.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1772.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1777.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1785.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1802.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1805.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1818.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1849.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1850.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1854.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1860.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1862.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1879.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1892.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1895.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1896.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1898.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1905.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1916.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1921.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1923.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1932.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1946.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1951.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1952.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1961.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1979.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1984.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1988.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1993.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1995.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2000.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2010.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2033.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2075.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2084.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2096.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2106.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2111.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2123.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2136.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2137.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2140.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2141.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2144.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2147.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2160.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2174.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2176.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2199.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2210.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2217.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2220.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2225.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2231.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2243.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2250.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2280.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2288.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2303.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2306.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2307.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2317.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2343.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2345.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2346.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2348.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2358.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2362.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2364.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2367.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2368.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2383.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2399.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2419.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2446.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2461.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2466.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2472.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2479.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2481.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2492.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2494.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2503.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2507.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2510.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2533.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2543.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2551.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2554.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2561.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2590.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2597.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2632.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2637.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2649.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2656.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2662.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2669.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2688.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2698.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2711.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2713.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2723.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2728.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2731.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2755.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2761.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2764.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2794.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2797.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2813.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2845.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2849.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2858.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2861.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2881.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2907.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2912.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2913.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2946.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2959.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2988.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3013.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3031.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3041.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3046.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3062.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3067.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3078.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3095.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3116.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3122.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3133.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3154.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3159.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3170.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3190.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3196.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3209.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3214.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3218.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3238.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3295.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3298.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3299.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3303.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3306.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3308.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3322.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3329.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3339.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3360.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3367.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3371.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3380.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3387.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3391.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3405.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3427.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3436.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3439.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3449.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3462.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3465.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3488.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3498.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3501.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3513.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3524.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3525.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3528.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3536.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3540.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3544.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3575.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3582.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3595.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3610.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3612.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3613.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3616.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3618.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3626.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3638.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3639.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3641.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3650.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3660.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3661.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3671.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3679.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3692.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3693.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3694.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3700.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3702.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3713.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3716.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3718.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3730.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3736.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3738.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3743.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3758.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3768.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3769.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3780.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3784.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3798.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3800.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3803.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3809.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3831.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3851.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3854.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3855.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3856.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3865.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3866.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3876.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3884.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3889.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3902.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3904.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3918.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3944.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3953.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3954.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3969.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3977.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3982.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3997.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4011.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4012.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4019.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4027.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4039.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4041.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4043.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4046.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4051.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4055.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4056.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4073.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4078.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4096.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4105.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4107.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4112.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4115.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4118.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4122.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4140.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4160.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4168.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4170.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4172.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4175.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4189.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4202.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4215.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4221.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4268.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4269.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4273.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4279.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4285.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4286.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4294.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4297.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4304.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4349.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4354.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4360.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4373.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4376.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4377.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4378.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4381.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4382.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4383.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4392.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4422.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4426.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4430.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4446.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4450.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4459.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4461.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4467.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4485.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4489.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4506.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4521.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4523.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4526.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4541.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4602.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4609.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4610.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4620.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4626.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4631.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4634.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4650.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4658.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4672.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4676.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4689.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4745.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4767.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4771.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4774.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4798.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4817.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4821.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4826.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4829.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4845.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4864.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4866.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4883.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4884.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4886.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4888.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4889.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4891.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4898.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4899.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4905.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4923.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4932.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4955.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4956.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4974.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4976.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4977.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4980.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4990.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5001.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5007.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5012.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5023.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5050.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5051.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5056.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5061.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5073.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5080.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5099.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5107.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5134.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5140.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5143.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5145.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5146.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5161.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5171.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5196.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5205.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5211.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5219.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5226.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5270.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5284.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5314.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5316.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5322.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5337.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5359.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5364.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5368.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5370.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5384.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5392.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5405.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5409.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5422.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5427.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5434.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5437.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5444.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5446.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5455.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5470.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5471.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5474.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5479.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5489.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5497.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5499.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5509.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5524.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5547.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5553.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5560.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5567.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5585.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5590.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5591.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5598.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5601.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5611.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5622.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5627.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5657.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5667.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5684.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5698.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5704.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5707.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5709.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5715.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5741.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5747.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5758.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5759.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5761.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5773.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5774.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5785.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5790.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5799.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5813.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5814.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5853.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5886.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5894.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5896.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5913.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5923.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5924.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5931.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5950.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5956.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5959.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5966.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5967.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5974.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5976.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5981.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5992.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6000.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6009.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6016.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6018.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6032.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6044.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6070.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6108.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6118.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6120.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6128.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6130.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6176.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6181.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6189.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6198.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6201.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6209.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6213.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6234.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6236.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6247.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6266.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6286.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6310.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6312.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6314.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6318.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6325.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6327.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6343.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6346.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6370.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6376.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6380.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6395.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6403.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6411.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6415.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6427.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6435.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6439.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6443.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6447.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6456.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6462.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6463.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6485.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6511.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6514.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6522.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6524.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6528.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6535.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6539.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6568.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6591.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6603.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6609.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6617.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6630.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6634.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6655.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6665.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6674.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6676.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6677.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6682.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6684.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6697.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6703.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6714.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6727.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6742.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6748.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6761.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6778.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6782.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6801.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6817.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6820.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6828.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6832.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6862.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6866.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6868.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6879.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6914.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6925.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6939.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6940.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6945.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6946.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6950.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6962.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6975.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6981.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6993.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7014.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7016.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7017.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7062.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7079.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7097.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7098.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7100.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7102.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7109.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7115.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7116.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7117.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7119.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7127.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7130.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7132.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7136.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7158.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7164.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7168.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7186.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7197.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7205.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7206.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7208.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7211.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7217.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7226.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7227.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7238.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7254.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7272.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7283.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7291.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7292.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7297.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7306.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7312.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7317.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7319.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7340.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7343.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7356.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7365.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7387.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7392.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7481.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7488.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7490.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7491.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7496.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7509.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7536.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7539.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7547.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7553.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7579.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7583.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7592.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7598.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7649.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7653.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7672.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7675.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7678.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7680.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7682.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7688.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7733.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7740.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7744.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7760.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7770.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7776.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7777.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7781.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7790.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7793.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7798.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7799.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7801.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7804.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7816.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7833.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7837.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7849.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7852.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7855.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7856.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7867.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7877.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7915.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7918.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7921.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7926.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7931.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7938.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7941.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7948.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7958.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7982.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7986.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7988.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8021.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8022.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8025.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8042.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8044.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8050.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8054.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8056.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8078.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8089.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8091.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8110.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8112.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8117.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8120.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8133.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8156.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8159.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8163.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8179.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8180.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8199.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8204.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8218.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8234.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8241.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8249.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8251.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8263.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8277.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8282.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8290.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8292.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8309.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8315.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8337.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8344.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8349.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8361.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8386.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8399.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8402.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8416.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8420.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8421.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8448.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8459.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8465.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8467.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8473.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8484.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8489.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8497.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8503.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8507.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8519.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8534.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8536.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8542.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8543.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8551.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8568.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8569.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8581.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8585.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8586.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8592.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8594.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8605.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8613.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8623.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8624.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8639.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8646.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8659.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8680.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8689.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8719.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8724.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8754.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8756.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8761.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8789.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8791.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8797.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8826.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8848.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8882.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8889.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8895.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8896.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8941.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8945.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8949.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8962.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8968.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8973.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8980.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8984.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9002.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9006.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9011.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9018.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9019.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9025.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9039.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9060.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9062.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9080.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9091.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9092.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9093.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9101.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9104.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9108.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9129.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9136.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9148.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9154.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9163.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9164.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9172.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9178.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9191.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9194.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9196.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9200.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9221.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9230.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9258.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9266.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9289.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9302.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9356.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9358.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9360.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9362.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9388.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9400.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9403.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9412.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9421.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9424.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9425.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9431.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9433.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9443.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9444.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9447.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9451.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9494.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9512.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9516.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9517.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9520.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9536.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9546.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9552.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9556.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9563.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9593.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9602.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9618.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9634.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9639.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9674.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9675.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9677.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9683.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9699.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9713.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9715.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9716.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9725.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9734.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9739.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9775.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9783.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9788.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9790.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9794.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9801.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9806.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9807.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9818.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9822.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9840.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9847.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9849.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9878.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9891.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9903.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9911.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9915.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9917.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9927.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9929.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9936.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9945.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9953.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9974.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9998.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10003.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10005.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10006.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10020.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10022.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10027.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10047.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10064.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10081.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10089.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10102.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10109.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10111.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10112.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10138.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10152.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10156.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10164.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10196.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10211.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10217.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10233.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10246.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10260.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10270.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10296.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10305.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10308.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10321.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10323.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10330.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10339.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10341.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10344.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10345.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10360.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10369.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10372.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10385.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10400.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10406.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10411.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10415.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10417.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10433.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10436.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10445.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10471.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10472.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10474.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10475.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10479.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10495.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10501.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10509.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10514.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10527.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10548.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10552.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10561.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10563.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10570.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10586.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10590.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10595.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10605.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10607.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10614.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10616.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10619.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10645.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10666.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10672.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10691.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10696.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10713.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10716.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10729.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10731.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10734.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10744.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10752.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10762.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10773.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10774.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10777.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10783.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10794.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10806.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10810.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10814.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10816.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10817.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10818.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10848.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10862.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10863.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10866.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10905.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10934.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10976.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10977.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10988.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10996.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10998.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11003.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11012.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11014.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11015.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11022.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11040.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11041.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11063.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11066.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11069.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11070.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11076.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11080.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11086.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11107.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11109.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11119.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11137.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11176.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11187.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11225.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11242.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11252.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11305.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11310.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11316.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11324.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11326.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11340.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11351.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11352.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11361.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11381.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11398.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11413.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11423.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11426.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11429.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11430.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11432.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11441.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11444.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11446.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11460.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11463.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11468.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11469.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11470.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11471.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11489.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11490.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11500.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11542.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11557.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11577.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11584.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11589.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11593.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11595.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11596.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11603.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11605.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11607.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11612.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11613.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11615.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11630.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11632.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11664.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11675.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11684.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11705.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11706.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11714.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11722.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11736.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11770.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11775.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11776.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11815.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11823.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11828.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11834.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11846.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11854.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11860.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11874.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11942.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11943.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11952.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11957.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11962.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11971.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11978.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11997.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11998.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12003.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12005.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12012.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12026.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12040.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12057.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12081.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12083.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12084.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12092.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12098.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12106.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12118.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12123.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12142.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12184.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12197.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12212.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12213.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12215.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12235.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12248.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12259.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12262.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12263.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12271.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12305.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12313.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12343.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst14.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst21.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst22.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst34.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst37.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst40.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst43.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst48.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst49.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst55.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst60.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst61.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst62.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst71.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst73.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst79.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst81.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst83.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst100.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst149.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst157.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst158.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst162.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst186.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst196.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst220.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst237.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst243.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst247.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst249.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst250.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst255.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst263.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst266.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst275.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst280.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst283.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst295.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst303.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst311.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst328.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst338.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst348.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst350.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst353.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst374.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst376.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst390.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst396.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst436.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst451.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst454.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst492.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst498.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst500.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst535.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst538.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst549.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst550.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst554.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst557.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst568.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst581.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst587.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst591.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst602.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst613.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst616.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst617.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst641.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst642.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst652.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst686.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst696.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst703.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst704.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst712.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst718.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst720.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst731.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst736.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst758.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst774.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst776.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst789.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst814.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst824.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst828.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst833.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst838.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst842.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst847.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst849.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst850.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst857.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst863.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst871.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst875.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst880.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst885.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst889.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst892.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst899.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst905.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst916.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst929.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst959.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst961.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst43.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst95.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst203.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst228.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst232.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst245.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst379.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst970.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst990.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1001.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1006.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1008.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1042.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1043.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1046.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1054.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1059.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1060.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1061.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1064.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1068.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1077.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1083.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1091.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1093.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1105.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1110.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1116.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1118.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1142.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1146.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1148.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1151.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1164.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1166.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1169.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1172.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1174.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1179.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1188.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1191.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1193.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1199.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1210.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1212.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1222.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1226.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1231.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1232.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1238.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1239.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1245.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1246.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1256.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1261.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1291.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1294.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1297.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1302.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1329.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1331.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1332.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1334.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1338.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1362.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1373.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1375.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1376.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1393.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1394.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1398.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1403.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1404.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1416.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1419.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1430.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1434.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1435.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1445.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1451.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1453.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1457.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1465.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1487.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1498.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1520.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1521.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1536.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1539.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1543.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1554.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1562.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1563.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1566.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1567.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1570.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1572.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1579.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1580.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1600.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1611.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1620.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1629.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1633.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1646.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1657.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1703.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1710.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1716.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1727.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1730.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1738.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1739.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1741.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1754.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1767.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1772.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1777.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1785.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1802.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1805.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1818.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1831.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1834.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1849.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1850.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1854.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1860.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1862.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1879.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1892.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1895.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1896.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1898.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1905.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1907.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1916.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1921.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1923.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1932.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1946.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1951.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1952.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1961.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1979.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1984.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1988.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1993.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1995.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2000.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2029.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2033.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2036.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2075.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2084.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2096.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2106.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2111.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2123.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2133.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2136.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2137.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2140.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2141.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2144.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2147.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2154.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2160.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2174.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2176.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2199.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2210.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2215.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2217.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2220.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2225.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2231.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2243.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2250.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2280.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2288.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2292.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2303.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2306.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2307.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2317.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2343.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2345.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2346.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2348.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2349.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2358.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2362.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2364.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2367.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2368.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2383.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2399.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2408.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2418.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2419.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2446.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2458.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2461.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2466.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2472.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2479.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2481.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2492.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2494.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2503.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2507.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2510.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2533.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2543.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2551.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2554.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2561.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2590.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2597.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2632.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2637.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2649.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2656.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2659.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2662.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2669.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2688.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2698.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2711.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2713.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2723.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2728.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2731.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2755.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2761.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2763.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2764.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2794.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2797.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2813.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2845.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2849.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2858.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2861.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2881.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2890.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2907.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2911.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2912.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2913.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2946.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2959.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2960.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2988.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3013.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3020.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3031.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3041.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3046.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3049.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3062.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3067.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3078.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3087.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3095.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3116.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3122.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3129.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3132.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3133.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3144.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3154.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3159.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3170.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3181.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3190.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3196.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3209.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3211.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3214.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3218.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3230.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3238.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3279.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3295.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3298.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3299.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3303.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3306.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3308.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3321.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3322.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3329.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3339.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3360.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3367.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3371.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3380.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3387.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3391.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3395.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3405.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3409.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3427.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3436.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3439.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3449.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3452.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3462.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3465.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3475.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3488.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3498.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3501.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3513.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3519.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3524.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3525.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3528.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3531.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3533.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3536.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3540.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3544.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3575.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3582.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3595.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3600.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3610.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3612.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3613.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3616.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3618.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3626.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3638.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3639.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3641.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3643.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3650.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3660.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3661.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3669.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3671.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3679.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3692.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3693.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3694.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3700.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3702.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3713.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3716.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3718.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3730.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3736.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3738.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3743.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3758.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3768.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3769.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3780.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3784.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3798.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3800.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3803.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3809.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3831.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3851.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3854.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3855.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3856.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3865.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3866.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3867.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3876.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3884.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3889.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3902.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3904.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3918.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3944.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3953.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3954.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3957.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3969.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3976.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3977.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3982.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3997.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4011.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4012.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4019.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4027.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4039.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4041.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4043.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4046.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4051.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4055.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4056.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4071.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4073.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4078.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4096.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4105.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4107.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4108.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4112.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4115.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4118.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4122.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4126.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4127.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4140.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4152.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4160.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4168.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4170.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4172.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4175.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4178.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4189.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4197.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4202.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4215.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4221.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4224.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4254.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4268.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4269.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4273.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4279.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4285.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4286.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4294.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4297.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4304.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4325.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4349.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4354.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4360.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4373.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4375.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4376.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4377.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4378.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4381.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4382.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4383.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4392.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4422.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4426.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4430.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4443.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4446.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4450.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4459.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4461.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4467.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4474.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4485.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4489.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4506.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4517.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4521.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4523.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4526.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4541.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4602.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4609.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4610.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4613.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4620.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4624.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4626.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4631.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4634.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4650.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4658.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4668.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4672.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4676.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4687.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4689.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4699.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4739.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4745.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4767.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4771.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4774.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4778.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4793.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4798.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4799.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4817.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4821.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4826.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4829.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4837.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4843.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4844.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4845.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4864.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4866.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4883.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4884.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4886.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4888.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4889.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4891.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4898.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4899.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4905.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4915.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4923.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4932.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4955.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4956.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4974.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4976.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4977.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4980.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4984.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4990.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5001.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5007.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5012.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5023.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5050.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5051.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5056.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5061.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5062.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5073.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5079.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5080.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5099.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5107.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5120.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5122.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5131.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5134.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5135.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5138.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5140.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5143.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5145.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5146.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5161.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5171.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5173.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5182.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5196.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5205.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5211.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5216.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5219.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5226.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5254.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5270.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5284.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5296.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5299.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5310.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5314.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5316.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5322.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5333.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5334.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5337.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5359.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5364.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5368.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5370.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5382.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5384.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5392.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5405.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5409.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5422.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5425.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5427.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5434.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5437.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5444.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5446.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5454.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5455.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5459.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5470.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5471.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5474.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5479.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5480.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5489.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5497.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5499.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5502.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5509.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5524.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5527.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5547.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5553.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5560.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5567.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5585.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5590.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5591.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5598.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5601.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5611.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5622.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5627.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5633.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5635.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5640.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5657.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5667.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5676.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5684.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5695.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5698.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5704.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5707.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5709.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5715.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5725.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5735.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5741.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5745.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5747.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5758.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5759.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5761.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5773.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5774.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5785.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5790.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5799.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5813.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5814.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5851.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5853.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5886.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5894.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5896.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5908.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5913.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5915.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5923.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5924.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5931.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5944.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5950.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5956.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5959.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5966.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5967.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5974.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5976.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5981.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5986.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5992.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5995.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6000.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6004.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6009.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6016.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6018.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6029.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6032.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6044.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6063.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6069.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6070.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6075.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6108.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6118.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6119.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6120.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6128.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6130.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6176.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6178.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6181.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6189.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6198.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6201.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6209.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6213.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6225.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6234.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6235.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6236.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6239.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6244.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6247.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6266.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6268.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6286.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6301.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6310.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6312.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6314.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6318.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6321.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6325.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6327.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6343.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6345.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6346.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6370.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6372.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6376.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6380.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6394.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6395.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6399.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6403.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6406.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6411.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6413.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6415.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6424.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6427.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6429.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6435.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6439.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6443.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6447.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6456.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6462.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6463.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6466.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6477.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6483.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6485.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6511.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6514.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6522.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6524.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6528.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6535.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6539.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6541.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6543.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6564.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6568.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6573.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6576.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6582.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6585.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6591.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6603.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6609.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6610.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6617.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6630.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6634.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6636.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6648.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6655.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6665.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6674.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6676.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6677.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6678.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6682.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6684.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6688.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6697.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6703.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6714.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6722.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6727.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6730.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6742.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6748.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6750.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6759.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6761.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6778.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6782.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6783.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6796.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6798.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6801.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6817.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6820.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6828.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6832.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6835.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6853.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6862.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6866.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6868.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6873.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6879.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6914.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6920.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6924.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6925.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6928.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6930.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6939.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6940.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6945.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6946.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6950.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6962.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6963.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6975.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6981.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6985.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6987.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6993.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7014.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7016.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7017.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7038.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7062.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7079.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7085.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7097.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7098.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7100.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7102.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7105.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7109.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7115.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7116.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7117.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7119.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7120.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7127.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7130.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7131.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7132.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7136.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7139.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7145.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7158.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7164.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7168.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7186.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7188.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7197.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7205.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7206.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7208.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7211.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7217.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7219.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7226.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7227.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7238.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7250.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7254.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7264.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7272.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7283.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7291.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7292.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7297.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7298.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7300.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7306.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7312.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7317.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7319.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7340.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7343.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7356.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7365.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7366.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7387.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7392.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7397.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7428.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7433.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7448.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7458.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7481.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7488.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7490.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7491.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7496.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7506.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7509.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7536.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7539.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7543.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7547.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7553.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7571.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7577.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7579.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7583.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7589.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7592.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7596.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7598.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7623.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7649.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7653.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7664.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7672.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7675.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7678.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7680.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7682.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7688.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7690.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7729.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7732.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7733.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7740.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7744.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7748.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7749.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7760.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7762.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7770.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7776.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7777.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7781.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7790.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7791.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7793.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7798.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7799.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7801.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7802.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7804.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7816.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7833.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7835.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7837.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7839.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7849.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7852.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7855.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7856.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7867.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7877.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7885.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7915.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7917.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7918.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7921.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7926.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7931.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7933.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7938.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7941.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7943.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7948.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7955.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7958.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7965.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7967.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7982.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7986.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7988.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8003.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8021.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8022.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8025.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8030.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8035.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8042.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8044.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8050.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8054.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8056.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8063.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8078.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8084.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8089.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8091.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8110.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8111.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8112.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8117.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8120.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8133.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8156.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8159.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8163.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8179.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8180.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8199.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8204.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8218.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8233.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8234.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8241.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8243.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8249.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8251.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8260.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8263.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8277.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8282.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8290.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8292.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8300.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8302.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8309.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8315.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8336.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8337.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8344.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8349.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8361.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8364.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8367.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8372.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8386.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8388.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8390.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8399.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8400.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8402.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8416.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8418.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8420.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8421.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8448.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8459.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8462.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8465.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8467.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8468.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8473.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8482.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8484.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8489.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8497.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8503.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8507.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8519.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8522.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8526.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8534.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8536.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8538.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8542.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8543.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8551.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8568.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8569.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8572.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8573.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8579.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8581.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8585.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8586.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8592.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8594.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8597.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8599.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8605.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8613.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8619.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8623.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8624.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8639.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8646.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8648.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8653.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8654.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8659.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8680.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8685.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8689.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8710.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8714.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8719.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8724.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8739.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8754.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8756.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8761.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8773.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8789.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8791.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8797.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8810.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8812.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8826.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8835.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8842.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8848.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8857.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8858.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8865.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8871.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8880.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8882.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8889.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8895.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8896.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8898.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8916.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8924.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8940.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8941.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8945.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8949.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8962.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8965.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8968.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8973.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8980.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8984.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9002.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9006.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9009.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9010.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9011.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9015.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9018.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9019.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9025.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9039.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9049.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9060.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9062.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9080.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9091.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9092.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9093.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9101.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9104.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9105.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9108.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9113.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9129.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9136.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9148.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9150.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9153.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9154.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9163.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9164.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9170.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9172.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9178.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9191.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9194.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9196.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9200.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9202.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9221.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9225.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9230.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9245.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9251.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9258.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9261.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9266.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9274.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9289.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9301.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9302.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9309.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9326.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9332.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9343.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9356.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9358.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9360.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9362.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9365.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9380.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9386.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9388.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9393.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9395.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9400.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9401.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9403.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9412.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9421.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9424.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9425.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9431.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9433.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9438.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9440.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9443.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9444.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9447.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9451.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9468.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9494.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9497.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9512.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9516.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9517.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9518.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9520.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9526.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9533.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9536.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9546.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9552.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9556.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9562.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9563.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9565.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9593.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9594.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9602.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9618.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9628.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9633.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9634.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9639.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9659.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9671.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9672.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9673.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9674.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9675.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9677.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9683.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9699.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9701.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9711.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9713.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9715.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9716.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9725.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9734.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9735.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9739.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9744.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9768.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9775.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9781.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9783.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9786.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9788.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9790.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9794.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9800.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9801.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9806.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9807.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9814.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9818.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9822.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9840.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9841.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9847.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9849.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9878.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9890.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9891.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9893.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9901.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9903.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9911.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9915.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9917.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9919.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9927.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9929.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9936.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9945.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9953.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9974.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9983.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9991.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9994.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9998.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10003.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10005.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10006.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10008.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10020.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10022.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10027.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10047.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10051.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10053.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10064.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10078.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10081.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10085.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10088.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10089.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10101.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10102.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10103.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10109.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10111.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10112.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10114.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10124.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10126.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10127.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10128.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10138.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10152.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10156.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10164.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10169.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10181.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10182.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10187.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10196.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10211.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10217.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10226.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10227.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10233.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10246.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10260.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10266.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10270.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10278.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10289.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10296.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10301.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10305.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10308.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10320.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10321.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10323.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10327.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10328.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10330.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10339.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10340.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10341.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10344.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10345.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10357.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10359.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10360.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10369.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10372.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10375.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10385.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10386.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10400.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10402.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10406.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10411.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10414.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10415.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10417.xdti_28hc_10t_30_and2 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10418.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10425.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10433.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10436.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10445.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10449.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10450.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10459.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10471.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10472.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10474.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10475.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10479.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10491.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10493.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10495.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10501.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10509.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10514.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10527.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10531.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10541.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10545.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10548.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10552.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10561.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10563.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10570.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10571.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10586.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10590.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10595.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10605.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10607.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10614.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10616.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10619.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10627.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10638.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10640.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10645.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10657.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10666.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10672.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10691.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10692.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10696.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10697.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10700.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10707.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10708.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10713.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10716.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10717.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10719.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10723.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10729.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10731.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10734.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10742.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10744.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10749.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10751.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10752.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10757.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10762.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10766.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10773.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10774.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10777.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10783.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10789.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10793.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10794.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10806.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10808.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10810.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10814.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10816.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10817.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10818.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10832.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10836.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10848.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10852.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10858.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10860.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10862.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10863.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10866.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10869.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10875.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10878.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10887.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10905.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10909.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10913.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10930.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10934.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10947.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10958.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10970.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10976.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10977.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10988.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10996.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10998.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11003.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11012.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11014.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11015.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11020.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11022.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11023.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11039.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11040.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11041.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11045.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11054.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11057.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11059.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11063.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11066.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11069.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11070.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11071.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11072.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11076.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11080.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11082.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11086.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11099.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11102.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11107.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11109.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11119.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11121.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11137.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11142.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11144.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11150.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11176.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11180.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11187.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11210.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11225.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11242.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11249.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11252.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11262.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11275.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11285.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11287.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11299.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11305.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11310.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11311.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11316.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11320.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11324.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11326.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11333.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11334.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11340.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11351.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11352.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11361.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11365.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11381.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11393.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11396.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11397.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11398.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11413.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11423.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11426.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11429.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11430.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11431.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11432.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11441.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11444.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11446.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11449.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11453.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11456.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11460.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11463.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11464.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11468.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11469.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11470.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11471.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11478.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11486.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11489.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11490.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11499.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11500.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11503.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11513.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11514.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11520.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11524.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11527.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11542.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11549.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11557.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11562.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11574.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11575.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11577.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11584.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11589.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11593.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11595.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11596.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11603.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11605.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11607.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11612.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11613.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11615.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11617.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11619.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11620.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11628.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11630.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11632.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11635.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11648.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11660.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11664.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11675.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11680.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11683.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11684.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11687.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11697.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11705.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11706.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11714.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11722.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11731.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11736.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11756.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11765.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11766.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11768.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11770.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11771.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11775.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11776.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11780.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11787.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11805.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11815.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11821.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11823.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11824.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11827.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11828.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11831.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11834.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11836.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11840.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11846.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11854.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11859.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11860.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11872.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11873.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11874.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11882.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11894.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11905.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11912.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11923.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11929.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11933.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11941.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11942.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i31.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i32.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i33.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i34.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i35.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i36.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i37.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i38.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i39.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i40.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i41.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i42.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i43.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i44.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11943.x1i3.x1i2.x1i45.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11948.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11951.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11952.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11953.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11957.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11962.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11964.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11966.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11971.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11978.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11979.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11996.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11997.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11998.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11999.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12003.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12005.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12012.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12014.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12026.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12028.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12040.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12045.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12057.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12058.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12067.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12081.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12083.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12084.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12092.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12098.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12106.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12118.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12123.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12125.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12126.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12140.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12142.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12143.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12155.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12157.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12165.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12166.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12167.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12175.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12183.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12184.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12193.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12194.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12195.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12197.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12203.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12204.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12207.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12212.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12213.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12215.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12223.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12235.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12237.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12240.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12248.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12256.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12259.xdti_28hc_10t_30_and2 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12260.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12262.xdti_28hc_10t_30_and2 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12263.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12271.xdti_28hc_10t_30_and2 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12280.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12305.xdti_28hc_10t_30_and2 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12313.xdti_28hc_10t_30_and2 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12316.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12318.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12323.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12324.xdti_28hc_10t_30_and2 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12343.xdti_28hc_10t_30_and2 60.00 60.00

Toggle Coverage for Module : dti_and2
TotalCoveredPercent
Totals 5 3 60.00
Total Bits 10 6 60.00
Total Bits 0->1 5 3 60.00
Total Bits 1->0 5 3 60.00

Ports 5 3 60.00
Port Bits 10 6 60.00
Port Bits 0->1 5 3 60.00
Port Bits 1->0 5 3 60.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
VDD No No No INPUT
VSS No No No INPUT
Z Yes Yes Yes OUTPUT
A Yes Yes Yes INPUT
B Yes Yes Yes INPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%